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AgeCommit message (Expand)Author
2015-07-15dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass
2015-07-15dm: x86: minnowmax: Move PCI to use driver modelSimon Glass
2015-07-15x86: pci: Tidy up the generic x86 PCI driverSimon Glass
2015-07-15x86: queensbay: Change CPU_ADDR_BITS to 32Bin Meng
2015-07-15x86: Setup fixed range MTRRs for legacy regionsBin Meng
2015-07-15x86: queensbay: Change PCIe root ports' interrupt routingBin Meng
2015-07-15x86: Remove inline for lapic access routinesBin Meng
2015-07-15x86: Add I/O APIC register access routinesBin Meng
2015-07-15x86: Reduce PIRQ routing table sizeBin Meng
2015-07-15x86: Ignore function number when writing PIRQ routing tableBin Meng
2015-07-15x86: Write correct bus number for the irq routerBin Meng
2015-07-15x86: Clean up lapic codesBin Meng
2015-07-15x86: Move lapic_setup() call into init_bsp()Bin Meng
2015-07-15x86: Move MP initialization codes into a common placeBin Meng
2015-07-15x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng
2015-07-15x86: dm: Clean up cpu driversBin Meng
2015-07-15x86: fsp: Move FspInitEntry call to board_init_f()Bin Meng
2015-07-15x86: fsp: Load GDT before calling FspInitEntryBin Meng
2015-07-15x86: Add Kconfig options to be used by arch/x86/cpu/config.mkBin Meng
2015-06-04x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford
2015-06-04x86: qemu: Implement PIRQ routingBin Meng
2015-06-04x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng
2015-06-04x86: coreboot: Fix cosmetic issuesBin Meng
2015-06-04x86: qemu: Adjust VGA initializationBin Meng
2015-06-04x86: qemu: Enable legacy IDE I/O ports decodeBin Meng
2015-06-04x86: qemu: Turn on legacy segments decodeBin Meng
2015-06-04x86: Do sanity test on pirq table before writingBin Meng
2015-06-04x86: quark: Implement PIRQ routingBin Meng
2015-06-04x86: Refactor PIRQ routing supportBin Meng
2015-06-04x86: qemu: Add graphics supportBin Meng
2015-06-04x86: Support QEMU x86 targetsBin Meng
2015-04-30x86: Add a CPU driver for baytrailSimon Glass
2015-04-30x86: Allow CPUs to be set up after relocationSimon Glass
2015-04-30x86: Add multi-processor initSimon Glass
2015-04-30x86: Provide access to the IDTSimon Glass
2015-04-30x86: Store the GDT pointer in global_dataSimon Glass
2015-04-30x86: Disable -WerrorSimon Glass
2015-04-30x86: Remove unwanted MMC debuggingSimon Glass
2015-04-30x86: quark: Use reset_cpu()Simon Glass
2015-04-30x86: ivybridge: Use reset_cpu()Simon Glass
2015-04-30x86: Implement reset_cpu() correctly for modern CPUsSimon Glass
2015-04-30x86: link: Add PCH driver to support SPI FlashSimon Glass
2015-04-30x86: quark: Turn on legacy segments decodeBin Meng
2015-04-30x86: queensbay: Implement PIRQ routingBin Meng
2015-04-30x86: Write configuration tables in last_stage_init()Bin Meng
2015-04-30x86: Add a function to assign IRQ numbers to PCI deviceBin Meng
2015-04-30x86: queensbay: Avoid using PCH prefixBin Meng
2015-04-18Kconfig: Move CONFIG_BOOTSTAGE to KconfigSimon Glass
2015-04-18x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass
2015-04-18dm: x86: Add a uclass for a Platform Controller HubSimon Glass
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