summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2013-12-18sh: add support for sh7753evb boardYoshihiro Shimoda
The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-16Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini
2013-12-16Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)Masahiro Yamada
Convert like follows: CPU mpc83xx -> CONFIG_MPC83xx CPU mpc85xx -> CONFIG_MPC85xx CPU mpc86xx -> CONFIG_MPC86xx CPU mpc5xxx -> CONFIG_MPC5xxx CPU mpc8xx -> CONFIG_8xx CPU mpc8260 -> CONFIG_8260 CPU ppc4xx -> CONFIG_4xx CPU x86 -> CONFIG_X86 ARCH x86 -> CONFIG_X86 ARCH powerpc -> CONFIG_PPC Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-16common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot ↵Miao Yan
interface. The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware description mechanism. For PowerPC, the boot interface conforms to the ePAPR standard, which is: void (*kernel_entry)(ulong fdt_addr, ulong r4 /* 0 */, ulong r5 /* 0 */, ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */, ulong r8 /* 0 */, ulong r9 /* 0 */) For ARM, the boot interface is: void (*kernel_entry)(void *fdt_addr) Signed-off-by: Miao Yan <miao.yan@windriver.com> [trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC, missing extern ft_fixup_num_cores] Signed-off-by: Tom Rini <trini@ti.com>
2013-12-16blackfin: remove build warningSonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-16blackfin: fixing warning by including proper headersSonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-13PowerPC: merge commonly-defined flagsMasahiro Yamada
PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 were defined in all arch/powerpc/${CPU}/config.mk. This commit moves them to arch/powerpc/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13ARM:PXA: Correct tick_to_time / us_to_tick to use lldivTom Rini
Cc: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de>
2013-12-13ARM:zynq: Correct __udelay to use lldivTom Rini
Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Tom Rini <trini@ti.com>
2013-12-13Makefile: use two double-quotations as a pairMasahiro Yamada
Some editors such as Emacs can highlight source files. But their parser algorithm is not perfect. If you use one double-quotation alone, some editor cannot handle it nicely and mark source lines as a string by mistake. It is preferable to use two double-quotations as a pair. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-11powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040Prabhakar Kushwaha
The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16. So, update its value as default. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-12-11powerpc/t4240: Add a frequency setting case for fman1Shaohui Xie
A new valid setting case added for fman1, it uses platform frequency. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-12-10Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
2013-12-10Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
2013-12-10Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini
2013-12-09sandbox: spi: Add SPI emulation busMike Frysinger
This adds a SPI framework for people to hook up simulated SPI clients. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09sandbox: Rename sb_cmdline_option to sandbox_cmdline_optionSimon Glass
The new name is longer but more clearly related to sandbox. This is in a separate patch within the same series since some comments on the SPI series rely on it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
2013-12-09at91: switch coloured LED to gpio APIAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-09at91: redefine legacy GPIO PIN_BASEAndreas Bießmann
In order to get the very same value for legacy pin definitions and new gpio definitions set the legacy PIN_BASE to 0. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-09at91: add new gpio pin definitionsAndreas Bießmann
This patch define new names for GPIO pins on at91 devices. Follow up patches will convert the whole infrastructure to use these new definitions. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
2013-12-07arm: keep all sections in ELF fileAlbert ARIBAUD
Current LDS files /DISCARD/ a lot of sections when linking ELF files, causing diagnostic tools such as readelf or objdump to produce partial output. Keep all section at link stage, filter only at objcopy time so that .bin remains minimal. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-12-06ARM: align MVBAR on 32 byte boundaryMasahiro Yamada
The lower 5 bit of MVBAR is UNK/SBZP. So, Monitor Vector Base Address must be 32-byte aligned. On the other hand, the secure monitor handler does not need 32-byte alignment. This commit moves ".algin 5" directive to the correct place. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
2013-12-06Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-12-06Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-12-06Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini
2013-12-06arm: omap3: Enable clocks for peripherals only if they are usedMichael Trimarchi
This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-12-06arm: exynos: adds ifdef for spi bootMinkyu Kang
This patch fix following errors and warnings spl_boot.c: In function 'exynos_spi_copy': spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function) spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function) spl_boot.c: In function 'copy_uboot_to_ram': spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable] spl_boot.c: At top level: spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function] Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-12-06Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD
2013-12-06blackfin: Do not generate unused header bootrom-asm-offsets.hMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-06blackfin: If none ADI_GPIOX macro is defined, use ADI_GPIO1 as defaultSonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-05arm: exynos: remove the unused define.Jaehoon Chung
These defines didn't use anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-05arm: exynos/goni: fix the return type for s5p_mmc_initJaehoon Chung
The "int" type is right. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-04powerpc/mpc8349: Use generic mpc85xx DDR driverYork Sun
MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun@freescale.com>
2013-12-04T4240: Address T4240/T4160 Rev2.0 DDR clock changeZang Roy-R61911
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-12-04powerpc/corenet: CPC1 speculation disableDave Liu
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-12-04pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAMHardik Patel
Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
2013-12-04davinci: fix Master Priority Registers locationViktar Palstsiuk
MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk@promwad.com>
2013-12-04arm: omap3: Add uart4 omap3 adddressMichael Trimarchi
This patch add the OMAP34XX_UART4 memory address Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2013-12-04ARM: OMAP5+: Remove unnecessary EFUSE settingsLokesh Vutla
Certain EFUSE settings were recommended for the first four lots of OMAP5 ES1.0 silicon. These are not applicable for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings. Reported-by: Griffis, Brad <bgriffis@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-04ARM: DRA7xx: Add PRCM and Control information for SATARoger Quadros
Adds the necessary PRCM and Control register information for SATA on DRA7xx. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: OMAP5: Add SATA platform glueRoger Quadros
Add platform glue logic for the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: OMAP5: Add PRCM and Control information for SATARoger Quadros
Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: OMAP5: Add Pipe3 PHY driverRoger Quadros
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039SRICHARAN R
When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04ARM: DRA: EMIF: Change DDR3 settings to use hw levelingSRICHARAN R
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04ARM: DRA7: Add is_dra7xx cpu check definitionSRICHARAN R
A generic is_dra7xx cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04am33xx: Stop modifying certain EMIF4D registersTom Rini
Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
2013-12-04ARM: OMAP4: Fix bug in omap4470_volts structLubomir Popov
The struct incorrectly referenced SMPS1 for all three power domains. Fixed this by using SMPS2 and SMPS5 as appropriate. Add some comments and choose voltage values that correspond to voltage selection codes. Signed-off-by: Lubomir Popov <l-popov@ti.com>
2013-12-04cm_t335: add cm_t335 board supportIlya Ledvich
Add cm_t335 board directory, config file. Enable build. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> [trini: Adapt Makefile] Signed-off-by: Tom Rini <trini@ti.com>
2013-12-03socfpga: Adding Freeze Controller driverChin Liang See
Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>