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2017-03-15board: Add STMicroelectronics STiH410-B2260 supportPatrice Chotard
This is a 96Board compliant board based on STiH410 SoC: - 1GB DDR - On-Board USB combo WiFi/Bluetooth RTL8723BU with PCB soldered antenna - Ethernet 1000-BaseT - SATA - HDMI - 2 x USB2.0 type A - 1 x USB2.0 type micro-AB - SD card slot - High speed connector (SD/I2C/USB interfaces) - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-15STiH410-B2260: Add device treePatrice Chotard
This device tree has been extracted from v4.9 kernel Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-15STiH410: Add STi SDHCI driverPatrice Chotard
Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-03-15gpio: do not include <asm/arch/gpio.h> for ARCH_STIPatrice Chotard
As no gpio.h is defined in arch/arm/include/asm/arch-stih410, to avoid compilation failure, do not include asm/arch/gpio.h. This is needed for example when including sdhci.h, which include asm/gpio.h>. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-15STiH410: Add STi serial driverPatrice Chotard
This patch adds support to ASC (asynchronous serial controller) driver, which is basically a standard serial driver. This IP is common across other STMicroelectronics SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-15arm: Add support for STMicroelectronics STiH410 socPatrice Chotard
The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU part of the STiH407 family. It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-15armv7m: Add SysTick timer driverPhil Edworthy
The SysTick is a 24-bit down counter that is found on all ARM Cortex M3, M4, M7 devices and is always located at a fixed address. The number of reference clock ticks that correspond to 10ms is normally defined in the SysTick Calibration register's TENMS field. However, on some devices this is wrong, so this driver allows the clock rate to be defined using CONFIG_SYS_HZ_CLOCK. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-03-15arm: omap3: Bring back ARM errata workaround 725233Siarhei Siamashka
The workaround for ARM errata 725233 had been lost since commit 45bf05854bc94e (armv7: adapt omap3 to the new cache maintenance framework). Bring it back in order to avoid very difficult to reproduce, but actually encountered in the wild CPU deadlocks when running software rendered X11 desktop on OMAP3530 hardware. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Migrate to Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-15arm: omap3: Compile clock.c with -marm option to unbreak OMAP3530Siarhei Siamashka
Boards with OMAP3530 SoC fail to boot since commit bd2c4522c26d5 ("ti: armv7: enable EXT support in SPL (using ti_armv7_common.h)") because it enabled the use of Thumb2 for the SPL. Experiments have shown that the deadlock happens in the prcm_init() function from 'arch/arm/mach-omap2/omap3/clock.c'. This patch enforces the compilation of clock.c source file in ARM mode and makes the deadlock disappear. We are yet to figure out the root cause of the problem. Still this is somewhat better than having non-bootable boards for years. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-13ARM: dts: uniphier: more re-sync DT with LinuxMasahiro Yamada
For better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-13ARM: dts: uniphier: fix no unit name warningsMasahiro Yamada
Fix warnings reported when built with W=1, by DTC 1.4.2 or later: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-13ARM: dts: uniphier: remove skeleton.dtsi inclusionMasahiro Yamada
Linux Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated") declared that skeleton.dtsi was deprecated. Move the memory node below to suppress warnings of FDTGREP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-13ARM: uniphier: set DRAM_SPARSE flag for LD21 boardsMasahiro Yamada
Commit 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from board parameters") accidentally unset the DRAM_SPARSE flag, and changed the physical map of the DRAM channels. Revive the original behavior. Fixes: 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from board parameters") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Shunji Sato <sato.shunji@socionext.com>
2017-03-12arm: omap-common: Fix typo in CONFIG_OMAP54XX guardMatthijs van Duin
Some initialization was unintentionally being skipped on omap5. Fixes: f5af0827f276 ("arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX") Signed-off-by: Matthijs van Duin <matthijsvanduin@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-12arm: OMAP2+: nandecc: propagate error to command return statusLadislav Michl
Currently nandecc returns zero even if underlaying omap_nand_switch_ecc function fails. Fix that by propagating error returned to command return value. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-10ARM: Migrate errata to KconfigTom Rini
This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-10omap4: Migrate to using implyTom Rini
Move the default y options under arch/arm/mach-omap2/omap4/Kconfig to be using imply instead in arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-10omap3: Migrate to using implyTom Rini
Move the default y options under arch/arm/mach-omap2/omap3/Kconfig to be using imply instead in arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-10TI: Migrate board/ti/common/Kconfig to implyTom Rini
The option that we had set in board/ti/common/Kconfig as default y are best done with imply under the appropriate main Kconfig option instead. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-10am335x_evm: Switch to using imply keywordTom Rini
These particular SPL options are part of what the ROM provides, but for compatibility with how we have previously used them, move them to being implied by the board being selected. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-10do_smhload: fix return codeRyan Harkin
do_smhload was using a ulong to store the return value from smh_load_file. That returns an int, where -1 indicates an error. As a ulong will never be negative, smh_load_file errors were not detected and so_smhload always returned zero. Also, when errors were spotted, do_smhload was returning 1, rather than the enumeration CMD_RET_FAILURE (which is also 1). Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-03-09Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigsTom Rini
In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-02armv8: spl: Call spl_relocate_stack_gd for ARMv8Philipp Tomsich
As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-02armv5te: make 'ret lr' produce iinterworking 'bx lr'Albert ARIBAUD
Current ARM assembler helper for the 'return to caller' pseudo-instruction turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain in its current ARM state even when the routine doing the 'ret' was called from Thumb-1 state, triggering an undefined instruction exception. This causes early run-time failures in all boards compiled using the Thumb-1 instruction set (for instance the Open-RD family). ARMv5TE supports 'bx lr' which properly implements interworking and thus correctly returns to Thumb-1 state from ARM state. This change makes 'ret lr' turn into 'bx lr' for ARMv5TE. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2017-02-27arm: mach-omap2: Flush cache after FIT post-processing imageAndrew F. Davis
After we authenticate/decrypt an image we need to flush the caches as they may still contain bits of the encrypted image. This will cause failures if we attempt to jump to this image. Reported-by: Yogesh Siraswar<yogeshs@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-02-23ARM: uniphier: set up charge pump current for MPLL of LD11 SoCMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23ARM: uniphier: add simple eMMC load APIs instead of ROM APIMasahiro Yamada
Re-use of routines embedded in the Boot ROM requires a function pointer table for each SoC. This is not nice in terms of the maintainability in a long run. Implement simple eMMC load APIs that are commonly used for LD11, LD20, and hopefully future SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20Masahiro Yamada
For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoCKotaro Hayashi
If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: remove dram_nr_ch from board parametersMasahiro Yamada
This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: rework spl_boot_device() and related codeMasahiro Yamada
The current implementation has ugly switch statements here and there, and duplicates similar code. Rework it using table lookups for SoC data and reduce code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: move spl_boot_mode() to a separate fileMasahiro Yamada
The spl_boot_mode() is unrelated to the other code in this file. Besides, this function is only called from common/spl/spl_mmc.c, so it is reasonable to guard with CONFIG_SPL_MMC_SUPPORT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: move MMC code to a separate fileMasahiro Yamada
Currently, arch/arm/mach-uniphier/boot-mode/boot-mode.c is messed up with unrelated code; there is no reason why the "mmcsetn" command must be placed in this file. Split out the MMC code into arch/arm/mach-uniphier/mmc-first-dev.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: dts: uniphier: drop u-boot, dm-pre-reloc from system-bus pinctrl nodeMasahiro Yamada
Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), SPL does not need pin-mux settings for the System Bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: remove DRAM base address from board parametersMasahiro Yamada
The base address of each DRAM channel can be calculated from other parameters, so does not need hard-coding. What we need is the size of each DRAM channel and DRAM_SPARSE flag to decide the start address of DRAM channel 1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: print Support Card info very lateMasahiro Yamada
Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), the System Bus is initialized by board_init(). The show_board_info() is called from board_init_f() by default, so the revision register of the Micro Support Card may not be accessed at this point. Show its revision after the System Bus is initialized. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: skip memreserve of unused DRAM bank of LD20Masahiro Yamada
Now the "for" loop here iterates on the detected memory banks. It must skip unused DRAM banks. Fixes: c995f3a3c526 ("ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: correct spelling of "invalid"Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is setMasahiro Yamada
If SG_MEMCONF_CH2_DISABLE bit is set, the DRAM channel 2 is unused. The register settings for the ch2 should be ignored. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-22ARM: uniphier: revive accidentally removed dcache_disable()Masahiro Yamada
Commit a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") accidentally dropped dcache_disable() call. Since then, the SPL of LD11 and LD20 failed to load U-Boot proper. Fixes: a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-21x86: Intel MID platforms has no microcode updateAndy Shevchenko
There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-21x86: zImage: add Intel MID platforms supportVincent Tinelli
Intel MID platform boards have special treatment, such as boot parameter setting. Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-21x86: Introduce INTEL_MID quirk optionAndy Shevchenko
Intel Mobile Internet Device (MID) platforms have special treatment in some cases, such as CPU enumeration or boot parameters configuration. Besides that several drivers are specifically developed for the IP blocks found on Intel MID platforms. Those drivers will be dependent to this option. Here we introduce specific quirk option for such cases. It is supposed to be selected by Intel MID platform boards, for example, Intel Edison. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-21x86: Force 32-bit jumps in interrupt handlersJ. Tang
Depending upon the compiler used, IRQ entries could vary in sizes. With GCC 5.x, the code generator will use short jumps for some IRQ entries but near jumps for others. For example, GCC 5.4.0 generates the following: $ objdump -d interrupt.o <snip> 00000207 <irq_18>: 207: 6a 12 push $0x12 209: eb 85 jmp 190 <irq_common_entry> 0000020b <irq_19>: 20b: 6a 13 push $0x13 20d: eb 81 jmp 190 <irq_common_entry> 0000020f <irq_20>: 20f: 6a 14 push $0x14 211: e9 7a ff ff ff jmp 190 <irq_common_entry> 00000216 <irq_21>: 216: 6a 15 push $0x15 218: e9 73 ff ff ff jmp 190 <irq_common_entry> This causes a problem in cpu_init_interrupts(), because the IDT setup assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit jumps, so this previously was not a problem. The fix is to force 32-bit near jumps for all entries within the inline assembly. This works for GCC 5.x, and 4.x was already using that form of jumping. Signed-off-by: Jason Tang <tang@jtang.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-17ARM: DRA7xx: Fix memory allocation overflowAndrew F. Davis
When using early malloc the allocated memory can overflow into the SRAM scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more dynamic allocation at the expense of a slightly smaller maximum image size. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-02-17SPL: Move SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to KconfigDalon Westergreen
Added SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION and SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig. Due to SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION being moved to Kconfig the board defconfigs for db-88f6820-gp_defconfig kc1_defconfig and sniper_defconfig need to be updated. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-02-17SPL: add support to boot from a partition typeDalon Westergreen
the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-02-17arm: omap5: Fix generation of reserved-memory DT nodeAndrew F. Davis
When the node 'reserved-memory' is not defined in the DT we fail to add needed properties. We also fail to move 'offs' to point to the new node. Fix these here. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-02-13Merge tag 'xilinx-fixes-for-v2017.03' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx fixes for v2017.03 - defconfig alignment - Topic.nl board updates - Minor microblaze comment fix
2017-02-12flash: complete CONFIG_SYS_NO_FLASH move with renamingMasahiro Yamada
We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is not completed. Finish this work by the tool. During this move, let's rename it to CONFIG_MTD_NOR_FLASH. Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH" than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will make the code more readable. Besides, negative meaning symbols do not fit in obj-$(CONFIG_...) style Makefiles. This commit was created as follows: [1] Edit "default n" to "default y" in the config entry in common/Kconfig. [2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH" [3] Rename the instances in defconfigs by the following: find . -path './configs/*_defconfig' | xargs sed -i \ -e '/CONFIG_SYS_NO_FLASH=y/d' \ -e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/' [4] Change the conditionals by the following: find . -name '*.[ch]' | xargs sed -i \ -e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \ -e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \ -e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \ -e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/' [5] Modify the following manually - Rename the rest of instances - Remove the description from README - Create the new Kconfig entry in drivers/mtd/Kconfig - Remove the old Kconfig entry from common/Kconfig - Remove the garbage comments from include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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