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2015-01-26Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-01-26ARM: zynq: List qspi, smc and nand baseaddressesMichal Simek
Add missing addresses to the list. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26ARM: zynq: List nand, qspi and jtag boot modesMichal Simek
Use full boot mode list in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26ARM: zynq: slcr: Dont modify the reserved bitsSiva Durga Prasad Paladugu
Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26ARM: zynq: ddrc: Setup half of memory only for ECC caseMichal Simek
Setup half of memory from ram_size for ECC case. All the time the same board can be configured with or without ECC. Based on ECC case detection use half of memory with the same configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26ARM: zynq: Remove empty lineMichal Simek
Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26ARM: zynq: Enable the Neon instructionsMichal Simek
Added the lowlevel_init to enable the Neon instructions. Initially the u-boot was causing undefined instruction exception if loaded through tcl, and working fine if loaded through FSBL. The exception was causing in convertion formula of given time to ticks. It was because, the Neon instructions were disabled and hence causing the undefined exception. In FSBL case, the FSBL was enabling the Neon instructions. Hence, added the lowlevel_init to enable the Neon instructions. Also enable neon instructions for non-xilinx toolchain. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26Merge branch 'master' of git://git.denx.de/u-boot-marvellTom Rini
2015-01-25ARM: kirkwood: fix cpu info for 6282 device idLuka Perkov
Signed-off-by: Luka Perkov <luka@openwrt.org> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Stefan Roese <sr@denx.de>
2015-01-24fsl/ls1021qds: Add deep sleep supporttang yuantian
Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD bootAlison Wang
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24arm: ls102xa: Update snoop settings for CCI-400Alison Wang
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24ARM: HYP/non-sec: Make variable gic_dist_addr as a local onetang yuantian
Defining variable gic_dist_addr as a globe one prevents some functions, which use it, from being used before relocation which is the case in the deep sleep resume process on Freescale SoC platforms. Besides, we can always get the GIC base address by calling get_gicd_base_address() without referring gic_dist_addr. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24crypto/fsl: Add fixup for crypto nodeRuchika Gupta
Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24arm: ls102xa: Add dummy gpio.h to enable CONFIG_OF_CONTROLRuchika Gupta
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. As a result, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. The right fix would be to split the lib/fdtdec.c to remove dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL for LS102x platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as defaultAlison Wang
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24arm/ls1021a: Add workaround for DDR erratum A008378York Sun
Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com>
2015-01-23powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200Masahiro Yamada
These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
2015-01-23powerpc: mpc5xxx: PM520 board supportMasahiro Yamada
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Josef Wagner <Wagner@Microsys.de>
2015-01-23powerpc: mpc5xxx: remove Total5200 board supportMasahiro Yamada
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boardsMasahiro Yamada
These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
2015-01-23powerpc: mpc85xx: remove P2020DS board supportMasahiro Yamada
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23powerpc: mpc85xx: remove P2020COME board supportMasahiro Yamada
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
2015-01-23powerpc: mpc85xx: remove P1_P2_RDB boardsMasahiro Yamada
These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2015-01-23powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS supportMasahiro Yamada
These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
2015-01-23Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini
2015-01-23Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2015-01-23Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2015-01-23Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2015-01-22ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2Masahiro Yamada
PH1-sLD3, PH1-LD6b have DDR channel 2. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: rename SG_MEMCONF_* macros for readabilityMasahiro Yamada
Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined by <linux/sizes.h> for readability. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: use <linux/sizes.h> for readabilityMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: remove non-sense inline directivesMasahiro Yamada
The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: add static to local functionsMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: fix IECTRL set code for PH1-Pro4Masahiro Yamada
For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: describe init_page_table shorterMasahiro Yamada
The assembly directive ".rept ... .endr" allows us to write the init_page_table much shorter. To make things further simpler, set the text and stack area as Normal Memory, and the other sections as Device attribute. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: fix comments in SoC Glue init functionMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-22ARM: UniPhier: remove __packed that causes a problem on GCC 4.9Masahiro Yamada
The DDR PHY training function, ddrphy_prepare_training() would not work if compiled with GCC 4.9. The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h) is specified with __packed because it represents a hardware register mapping, but it turned out to cause a problem on GCC 4.9. If -mno-unaligned-access is specified (yes, it is in arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the __attribute__((packed)) and generates extra instructions to perform the memory access in a way that does not cause unaligned access. (Actually it is not need here because the register base, the first argument of the ddrphy_prepare_training(), is always given with a 4-byte aligned address.) Anyway, as a result, readl() / writel() is divided into byte-wise accesses. The problem is that this hardware only accepts 4-byte register access. Byte-wise accesses lead to unexpected behavior. There are some options to avoid this problem. [1] Remove -mno-unaligned-access [2] Add __aligned(4) along with __packed to struct ddrphy [3] Remove __packed from struct ddrphy [1] solves the problem for ARMv7, but it does not for pre-ARMv6 and ARMv6-M architectures where -mno-unaligned-access is default. So, [1] does not seem reasonable in terms of code portability. Both [2] and [3] work well, but [2] seems too much. All the members of struct ddrphy have the u32 type. No padding would be inserted even if __packed is dropped. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com>
2015-01-22Merge branch 'next' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-01-22Merge branch 'phys_t' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-01-22sunxi: Hookup OTG USB controller supportHans de Goede
Hookup OTG USB controller support and enable the otg controller + USB-keyb on various tablets. This allows tablet owners to interact with u-boot without needing to solder a serial console onto their tablet PCB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sunxi: video: Use frontend for dma on sun4i to fix memory bandwidth problemsHans de Goede
Testing has shown that on sun4i the display backend engine does not have deep enough fifo-s causing flickering / tearing in full-hd mode due to fifo underruns. On sun4i use the display frontend engine to do the dma from memory, as the frontend does have deep enough fifo-s. As added advantage of this is that it results in much better memory bandwidth as it reduces the amount of dram bank switches, for more details see: http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html Note that this changes the pipeline searched for in the simplefb node, we can get away with doing this now, since no kernel has yet shipped with simplefb dtb nodes, and I will make sure to get a simplefb node with the new pipeline into 3.19 before it ships. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sunxi: Stop differentiating between 512M and 1G variants of the same boardHans de Goede
While working on adding more boards I noticed that we lack a config for the 512M cubieboard, and that some of the new boards which I want to add also have 512M and 1G variants, rather then adding 2 defconfig's for all of these, lets switch the exising boards which have both a 512M and 1024M variant over to the sun4i dram autoconfig code. This also drops the foo_RAMSIZE_defconfig variants of boards where we currently have 2 separate configs already. Note: 1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with a value other then its default for now, but we need this to be configurable to support some new boards with auto dram config. 2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match the defaults, this is done to make it more clear what values are used for a certain board. This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G variants, the dram autoconfig code has also been tested on a 512M mk802 (a defconfig for the mk802 is added in a later patch). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sunxi: mmc: Add support for sun9i (A80)Hans de Goede
The clocks on the A80 are hooked up slightly different, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sun9i: Add sun9i (A80) clock setup supportHans de Goede
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sun9i: Add clock_sun9i.h with ccu register layout for sun9iHans de Goede
Add a headerfile with the sun9i ccu register layout. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sun9i: Add cpu_sun9i.h with iomem definesHans de Goede
Add a headerfile with all the base addresses from the sun9i blocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sunxi: Rename cpu.h to cpu_sun4i.hHans de Goede
sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite different, so add a wrapper cpu.h which includes the right mach specific cpu_sun#i.h based on mach, like we already do with clock.h and dram.h . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headersHans de Goede
Which pll-s are available depends on the machine type, move the clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files so that we only declare what is actually available. e.g. clock_get_pll5p() is not available on sun6i / sun8i, and with sun9i we get a completely different set of plls. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22sunxi: Drop pll6 setting from clock_init_uartHans de Goede
As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>