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2017-03-29arc: dts: separate single axs10x.dts fileVlad Zakharov
We want to use the same device tree blobs in both Linux and U-Boot for ARC boards. Earlier device tree sources in U-Boot were very simplified and hadn't been updated for quite a long period of time. So this commit is the first step on the road to unified device tree blobs. First of all we re-organize device tree sources for AXS10X boards. As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and AXC003 cpu tiles respectively we add corresponding device tree source files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for cpu tiles and axs101.dts and axs103.dts to represent actual boards. Also we delete axs10x.dts as it is no longer used. One more important change - we add timer device to ARC skeleton device tree sources as both ARC700 and ARCHS cores contain such timer. We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree sources as it is referenced via phandle from timer node in common skeleton.dtsi file. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-29drivers: timer: Introduce ARC timer driverVlad Zakharov
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-29arm: mvebu: Add gdsys ControlCenter-Compact boardDirk Eibach
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x SOC. It boots from SPI-Flash but can be configured to boot from SD-card for factory programming and testing. On board peripherals include: - 2 x GbE - Xilinx Kintex-7 FPGA connected via PCIe - mSATA - USB3 host - Atmel TPM Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm: mvebu: AXP: Add possiblity to configure PEX detection pulse widthStefan Roese
Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: dts: Add device tree for ESPRESSOBin boardKonstantin Porotchkin
Initial DTS file for Marvell ESPRESSOBin comunity board based on Armada-3720 SoC. The Marvell ESPRESSOBin is a tiny board made by Globalscale and available on KickStarter site. It has dual core Armv8 Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM, mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0 interfaces, Gigabit Ethernet switch with 3 ports, micro-SD socket and two 46-pin GPIO connectors. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: a37xx: dts: Add pin control nodes to DTKonstantin Porotchkin
Add pin control nodes for North and South bridges to Armada-37xx DT Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: mvebu: Rename the db-88f3720 to armada-37xx platformKonstantin Porotchkin
Modify the file names and deifinitions relater to Marvell db-77f3720 board support. Convert these names to more generic armada-37xx platform for future addition of more boards based on the same SoC family. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: mvebu: dts: Add DTS file for MACCHIATOBin boardRabeeh Khoury
Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: mvebu: dts: Add i2c1 pin definitions to CPMKonstantin Porotchkin
Add i2c-1 pin mappings to CP0(master) DTSI file Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: mvebu: gpio: Add GPIO nodes to A8K family devicesKonstantin Porotchkin
Add GPIO nodes to AP-806 and CP-110-master DTSI files. Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-28arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2Bharat Bhushan
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they are behind SMMU. This patch defines the stream-ids for Chassis-2 devices. DPAA1 is reserved for future use. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Rewrite comment for stream IDsBharat Bhushan
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.hBharat Bhushan
The stream ID allocation for Chasis 3.0 devices can be shared among LS1088, LS2088 and LS2080. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND FlashHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl: PPA: add support PPA image loading from NAND and SDHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012AYingxi Yu
USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup. Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28board: freescale: ls2080a/ls2088a: Enable PPASantan Kumar
Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: add LS2088A series SoC pcie supportHou Zhiqiang
The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203Ashish kumar
This i2c errata only applies to LS2080A and its variants, namely LS2080A, LS2085A and LS2088A. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: dts: fsl-ls1012a: Change number of CS in SPI nodeSuresh Gupta
LS1012A has only one chip select for QSPI flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8:fsl-layerscape: Avoid RCWSR28 register hard-codingPrabhakar Kushwaha
SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28arm: fsl-layerscape: Move QSGMII wriop_init to SoC filePrabhakar Kushwaha
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8/fsl-layerscape: Update erratum A009635 implementationPriyanka Jain
Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl: Secure Boot: Enable IE (Key extention) FeatureUdit Agarwal
For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a verified table of public keys can be used. The latter feature is called IE Key Extension Feature. For Layerscape Chasis 3 based platforms, IE table is validated by Bootrom and address of this table is written in scratch registers 13 and 14 via PBI commands. Following are the steps describing usage of this feature: 1) Verify IE Table in ISBC phase using keys stored in fuses. 2) Install IE table. (To be used across verification of multiple images stored in a static global structure.) 3) Use keys from IE table, to verify further images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl-layerscape/ppa: cleanup ppa.hHou Zhiqiang
Moved the ifdef into ppa.h and removed the duplicated macros. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080AUdit Agarwal
Add header address for PPA to be validated during ESBC phase for LS2080A platform based on Layescape Chasis 3. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28i2c: lpc32xx: Move definitions to header fileLiam Beguin
Since the lpc32xx i2c driver does not yet support the devicetree bindings, this structure is also needed by the board file as the hardware description is done there. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-26reset: Add STi reset supportPatrice Chotard
This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-24Merge git://git.denx.de/u-boot-arcTom Rini
This replaces legacy arch/arc/lib/timer.c implementation and allows us to describe ARC Timers in Device Tree. Among other things that way we may properly inherit Timer's clock from CPU's clock s they really run synchronously.
2017-03-24arc: use timer driver for ARC boardsVlad Zakharov
This commit replaces legacy timer code with usage of arc timer driver. It removes arch/arc/lib/time.c file and selects CONFIG_CLK, CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default. Therefore we remove CONFIG_CLK option from less common axs101 and axs103 defconfigs. Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from axs10x.h, tb100.h and nsim.h configs files as it is no longer required. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-24arc: dts: separate single axs10x.dts fileVlad Zakharov
We want to use the same device tree blobs in both Linux and U-Boot for ARC boards. Earlier device tree sources in U-Boot were very simplified and hadn't been updated for quite a long period of time. So this commit is the first step on the road to unified device tree blobs. First of all we re-organize device tree sources for AXS10X boards. As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and AXC003 cpu tiles respectively we add corresponding device tree source files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for cpu tiles and axs101.dts and axs103.dts to represent actual boards. Also we delete axs10x.dts as it is no longer used. One more important change - we add timer device to ARC skeleton device tree sources as both ARC700 and ARCHS cores contain such timer. We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree sources as it is referenced via phandle from timer node in common skeleton.dtsi file. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-24drivers: timer: Introduce ARC timer driverVlad Zakharov
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-23arm: mvebu: Add gdsys ControlCenter-Compact boardDirk Eibach
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x SOC. It boots from SPI-Flash but can be configured to boot from SD-card for factory programming and testing. On board peripherals include: - 2 x GbE - Xilinx Kintex-7 FPGA connected via PCIe - mSATA - USB3 host - Atmel TPM Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm: mvebu: AXP: Add possiblity to configure PEX detection pulse widthStefan Roese
Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm64: dts: Add device tree for ESPRESSOBin boardKonstantin Porotchkin
Initial DTS file for Marvell ESPRESSOBin comunity board based on Armada-3720 SoC. The Marvell ESPRESSOBin is a tiny board made by Globalscale and available on KickStarter site. It has dual core Armv8 Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM, mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0 interfaces, Gigabit Ethernet switch with 3 ports, micro-SD socket and two 46-pin GPIO connectors. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm64: a37xx: dts: Add pin control nodes to DTKonstantin Porotchkin
Add pin control nodes for North and South bridges to Armada-37xx DT Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm64: mvebu: Rename the db-88f3720 to armada-37xx platformKonstantin Porotchkin
Modify the file names and deifinitions relater to Marvell db-77f3720 board support. Convert these names to more generic armada-37xx platform for future addition of more boards based on the same SoC family. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm64: mvebu: dts: Add DTS file for MACCHIATOBin boardRabeeh Khoury
Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm64: mvebu: dts: Add i2c1 pin definitions to CPMKonstantin Porotchkin
Add i2c-1 pin mappings to CP0(master) DTSI file Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23arm64: mvebu: gpio: Add GPIO nodes to A8K family devicesKonstantin Porotchkin
Add GPIO nodes to AP-806 and CP-110-master DTSI files. Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-21configs: am43xx_evm: Enable SPL_DMLokesh Vutla
Enable SPL_DM on all AM43xx based platforms Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-21ARM: AM43xx: Enable DM_I2C/SPI/ETHLokesh Vutla
Enable DM_I2C/SPI/ETH for all AM43XX based boards. Enable it using imply keyword so that a user can disable this when not needed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-03-21ARM: dts: am43xx: Add u-boot specific dtsiLokesh Vutla
Add u-boot specific dtsi for am43xx-gp-evm so that it will be used for SPL. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-03-21ARM: dts: OMAP5+: Add u-boot specific dtsiLokesh Vutla
Add u-boot specific dtsi so that this will be included automatically while building dts. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-03-21ARM: OMAP2+: define _image_binary_end to fix SPL_OF_CONTROLLokesh Vutla
To make SPL_OF_CONTROL work on OMAP2+ SoCs, _image_binary_end must be defined in the linker script along with CONFIG_SPL_SEPARATE_BSS. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-03-20board: ns2: Add support for Broadcom Northstar 2Jon Mason
Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k). The BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57 processors targeting a broad range of networking applications. Signed-off-by: Jon Mason <jon.mason@broadcom.com>
2017-03-20ARM: am43xx: fix SOC revision print outsTero Kristo
Currently, AM43xx just re-uses the version strings from AM33xx which is wrong; the actual values for AM43xx are different. Fix this by adding a separate version string array for AM43xx and use this instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-20ARM: k2g: setup PRU ethernet MAC addressesRoger Quadros
PRU ethernet MAC address range is present in the board EEPROM. Parse it and setup eth?addr environment variables. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-20ti: common: board_detect: Rename EEPROM scratch start macroLokesh Vutla
Non OMAP platforms i.e. Keystone will also need to use the board EEPROM helpers so let's make the macro platform independent. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-20ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macroRoger Quadros
GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index from the GPIO bank number and bank's GPIO offset number. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v0.10.2 at 2024-08-10 12:49:01 (GMT)