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2017-05-23armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-bootSantan Kumar
This patch adjusts memory map for images on LS2080ARDB and LS2080AQDS NOR flash as below Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043AAlison Wang
This patch is to adjust the memory mapping for FLash/SD card on LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN firmware load address, QE firmware load address, U-Boot start address on serial flash and environment address. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb: Add LS2081ARDB board supportPriyanka Jain
LS2081ARDB board is similar to LS2080ARDB board with few differences It hosts LS2081A SoC Default boot source is QSPI-boot It does not have IFC interface RTC and QSPI flash device are different It provides QIXIS access via I2C Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb: Add QSPI-boot supportPriyanka Jain
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23board: freescale: ls2080ardb: Enable SD interface for RevF boardPriyanka Jain
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-13Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2017-05-12arm: change tbu/l type to unsigned intPeng Fan
Change tbu/l type to unsigned int. >From the timer file for arm, "(((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;" is used, This piece code is based on tbu/tbl is 32bits, so change the type to unsigned int. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2017-05-12rk3036: Fix unused variable warningTom Rini
The variable grf is only referenced if EARLY_DEBUG is defined so move the declaration to be under the existing guard. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-12arm: amx3xx: Add support for early debugLokesh Vutla
For early debug, the following configs needs to be enabled: CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_OMAP=y CONFIG_DEBUG_UART_BASE=0x44e09000 CONFIG_DEBUG_UART_CLOCK=48000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12arm: omap5+: Add support for early debugLokesh Vutla
For early debug, the following configs needs to be enabled: CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_OMAP=y CONFIG_DEBUG_UART_CLOCK=48000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y For DRA7xx: CONFIG_DEBUG_UART_BASE=0x4806a000 For AM57xx: CONFIG_DEBUG_UART_BASE=0x48020000 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12arm: am33xx: Add support for mulitiple PLL input frequenciesLokesh Vutla
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12arm: am33xx: Fix MPU opp selectionLokesh Vutla
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data: MPU values for PG 2.0 and later(Package ZCZ and ZCE): ------------------------------------------------------- | | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 | ------------------------------------------------------- There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages. [1] http://www.ti.com/lit/ds/symlink/am3356.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12configs: convert CONFIG_SYS_MPUCLK to KconfigLokesh Vutla
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12stm32f7: configure mpu valid for f7 familyVikas Manocha
This configuration should be valid for all F7 family devices in general. Here is the regions info: - Region0 : 4GB : cacheable & executable. - Region1 : 512MB : text area : strogly ordered & executable. - Region2 : 512MB : peripherals : device memory & non-executable. - Region3 : 512MB : peripherals : device memory & non-executable. - Region4 : 512MB : cortexM area: strongly ordered & non-executable. Higher region number overrides the lower region configuration. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-12stm32: use armv7m MPU configuration supportVikas Manocha
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-12armv7m: add MPU configuration supportVikas Manocha
Cortex-M archs support option memory protection unit (MPU). MPU is used to set the memory types, attributes, access permissions for different regions, cache policies of the device. e.g. using MPU it is possible to configure memory region as device memory or strongly ordered, memory attributes like execute never, cache policies like write-back or write-through. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-12armv7m: correct mpu region size define for 8MB sizeVikas Manocha
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-12arvm7m: add cleanup before linux bootingVikas Manocha
Data cache memory needs to be disabled before handing over control to linux kernel. This patch populates the cleanup_before_linux stub. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-12armv7m: cache: add flush & invalidate all dcacheVikas Manocha
Add functionality to flush & invalidate all the dcache using the prototype declared in common header file. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add dummy functions for the not-enabled case] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-12boston: Setup memory ranges in FDT provided to LinuxPaul Burton
The boston memory map isn't suited to the simple "all memory starting from 0" approach that the MIPS arch_fixup_fdt() implementation takes. Instead we need to indicate the first 256MiB of DDR from 0 and the rest from 0x90000000. Implement ft_board_setup to do that. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-12boston: Move CM GCRs away from flashPaul Burton
Move the MIPS Coherence Manager (CM) Global Configuration Registers (GCRs) away from the region of the physical address space which the Boston board's parallel flash is found in, such that we can access all of flash without clobbering GCRs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-12MIPS: Make CM GCR base configurablePaul Burton
Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow defconfigs to set it. Provide the prompt in order to allow for that. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-12mips: bmips: add missing SFR NeufBox 4 configÁlvaro Fernández Rojas
Fixes commit a186d26, which missed including SFR NeufBox config from bmips Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12mips: bmips: bcm63268: fix brcm, bcm6328-mc sizeÁlvaro Fernández Rojas
Shrink brcm,bcm6328-mc size to avoid overlapping with other controllers Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12mips: bmips: bcm6328: fix brcm, bcm6328-mc sizeÁlvaro Fernández Rojas
Shrink brcm,bcm6328-mc size to avoid overlapping with other controllers Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12mips: bmips: bcm6358: fix brcm, bcm6358-mc sizeÁlvaro Fernández Rojas
Shrink brcm,bcm6358-mc size to avoid overlapping with other controllers Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12arm: am335x: Enable tiny printf in SPLLokesh Vutla
am335x_evm SPL is very close to its limit in SRAM space. Switch to use tiny printf to reclaim some size. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-12configs: am335x_evm: Enable SPL_DMLokesh Vutla
Enable SPL_DM on all AM335x based TI platforms. http://patchwork.ozlabs.org/patch/751300/ Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-12configs: am335x_evm: Use omap2 generic spl load scriptLokesh Vutla
No reason to use a separate load script for am33xx than using omap-common load script. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12dm: mmc: omap_hsmmc: Update to support of-platdataLokesh Vutla
This is to aid platforms that uses OF_PLATDATA. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-12spl: fdt: support for fdt fixup for falcon bootB, Ravi
Adding support for fdt fixup to update the memory node in device tree for falcon boot. This is needed for single stage or falcon bootmode, to pass memory configuration to kernel through DT memory node. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2017-05-12arch: arm: omap: Declare size of ddr very earlyLokesh Vutla
Declare the size of ddr very early in spl, so that this can be used to enable cache. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
2017-05-12arm: Support cache invalidateSimon Glass
At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-12arm: Correct signature for get_ticks()Simon Glass
This should be uint64_t to match its definition in common.h. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10Merge git://git.denx.de/u-boot-rockchipTom Rini
This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.
2017-05-10Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2017-05-10rockchip: dts: evb_rk3288: Add mipi display supportEric Gao
Add mipi dsi configuration for evb-rk3288 device tree. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: rk3288: grf: Add grf define for mipi dsiEric Gao
Add grf register define for rk3288 mipi dsi Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: dts: Add mipi dsi support for rk3399Eric Gao
Add dts config for mipi display, include vop, mipi controller, panel, backlight . And Enable rk808 for lcd_3v3 in another patch. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10rockchip: video: vop: Add mipi display mode for rk3399Eric Gao
Add mipi display mode for rk3399 vop, so that we can use mipi panel for display. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: video: Add mipi driver support for rockchip socEric Gao
Add basic driver for mipi display on rockchip soc platform. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: include: grf: Add GRF register declaration for mipi dsiEric Gao
Add GRF register declaration for mipi dsi. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10power: rk808: rename to rk8xxJacob Chen
Since this driver can be used for rk8xx series pmic, let's rename rk808 to rk8xx, to make it clear. Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./` Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
2017-05-10rockchip: tinker: set ethaddr in late initJonas Karlman
Set ethernet mac address in late init for Tinker Board, prevents getting a random mac address each boot. Read mac address from eeprom, first 6 bytes from m24c08@50. Same as /etc/init.d/rockchip.sh on Tinker OS. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add support for the HDMI I2C pinsPhilipp Tomsich
To add HDMI support for the RK3399, this commit provides the needed pinctrl functionality to configure the HDMI I2C pins (used for reading the screen's EDID). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: dts: add rk3399-firefly dtsKever Yang
Firefly-rk3399 is a bord from T-Firefly, you can find detail about it here: http://en.t-firefly.com/en/firenow/Firefly_RK3399/ This patch add basic node for the board and make it able to bring up. Peripheral/interfaces on board: - usb hub which connect to ehci controller; - UART2 debug - eMMC - PCIe - USB 3.0 HOST, type-C port - sdio, sd-card - HDMI - Ethernet - OPTICAL - WiFi/BT - MIPI CSI/DSI - IR - EDP/DP Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: dts: rk3399: sync with kernel dtsKever Yang
The kernel dts has update a lot since the first time we commit rk3399.dtsi, sync with kernel for further development. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: reserve memory for rk3399 ATF dataKever Yang
There are 3 regions used by rk3399 ATF: - bl31 code, located at 0x10000; - cortex-m0 code and data, located at 0xff8c0000; - bl31 data, located at 0xff8c1000 ~ 0xff8c4000; SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory for ATF data, or else there will be memory corrupt after SPL loads the ATF image. More detail about cortex-M0 code in ATF: https://github.com/ARM-software/arm-trusted-firmware/commit/ 8382e17c4c6bffd15119dfce1ee4372e3c1a7890 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add gmac io strength supportKever Yang
GMAC controller need to init the tx io driver strength to 13mA, just like the description in dts pinctrl node, or else the controller may only work in 100MHz Mode, and fail to work at 1000MHz mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v0.10.2 at 2024-11-12 16:08:20 (GMT)