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2018-01-29BCD data reading implementedvojo
2018-01-09M.2 SATA testedvojo
2017-12-27grapeboard BCD initial support and clean-upvojo
2017-12-19Grapeboard support addedvojo
2017-10-30armv8: fsl-layerscape: Fix MC reserved memory calculationYork Sun
In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-10-17armv8: Workaround for USB erratum A-009007 on LS1088ARan Wang
Suplements for patch 2e3dbee02915aaf75834747ff8753282118075dc to cover LS1088A: USB3PHY Observing Intjermittent Failure in Rx Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-10-11fsl: csu: enable ns access for PFECalvin Johnson
Enable non-secure access for PFE block. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11armv8: fsl-lsch2: configure pfe's scfg & dcfg registersCalvin Johnson
Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg registers of pfe. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structureCalvin Johnson
SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11armv8: fsl-lsch2: initialize pfe gemacCalvin Johnson
Call gemac_initialize to initialize both gemacs of pfe. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11armv8: fsl-layerscape: Add support of GPIO structurePrabhakar Kushwaha
Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-09-15armv8: fsl-layerscape: Fix some coding style problems in soc.cAlison Wang
This file has some coding style problems. Fix these to make the future updates easier. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-13ls1088aqds: Enable IFC and QIXIS in SPL imageSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-09-11armv8: fsl-layerscape: Add back L3 flushing for all exception levelsYork Sun
CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-11armv8/fsl-lsch2: correct QMAN clockHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-07board/freescale: Share qbman init between archsAhmed Mansour
This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Created new board/freescale/common/portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Added new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-09-04armv8: ls1088a: correct pcie fixup compatible stringHou Zhiqiang
LS1088A has the same PCIe controller as LS2088A, and the LS1088A used LS2088A PCIe compatible under Linux. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-04armv8: ls1088a: add PCIe dts nodeHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-04armv8: ls1088a: fix the MMU table for pcie config spaceHou Zhiqiang
The pcie config space of ls1088a is different from ls2080a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-03armv8: sec_firmware: Add support for loadables in FITSumit Garg
Enable support for loadables in SEC firmware FIT image. Currently support is added for single loadable image. Brief description of implementation: - Add two more address pointers (loadable_h, loadable_l) as arguments to sec_firmware_init() api. - Create new api: sec_firmware_checks_copy_loadable() to check if loadables node is present in SEC firmware FIT image. If present, verify loadable image and copies it to secure DDR memory. - Populate address pointers with secure DDR memory addresses where loadable is copied. Example use-case could be trusted OS (tee.bin) as loadables node in SEC firmware FIT image. Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-09-03armv8: layerscape: Allocate 66 MB DDR for secure memorySumit Garg
Change DDR allocated for secure memory from 2 MB to 66 MB. This additional 64 MB secure memory is required for trusted OS running in Trusted Execution Environment using ARMv8 TrustZone. Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-08-30armv8: fsl-layerscape: Fix final MMU table for QSPI and IFCSuresh Gupta
For QSPI and IFC addresses execution shouldn't be allowed when u-boot running from DDR. Revise the MMU final table to enforce execute-never bits. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
2017-08-30board: common: vid: Add support for LTC3882 voltage regulator chipPrabhakar Kushwaha
Restructures common driver to support LTC3882 voltage regulator chip. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2017-08-30armv8: lsch3: Add serdes and DDR voltage setupRajesh Bhagat
Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2017-08-29armv8: fsl: Use correct conditional compile for ls1012aRan Wang
According current code base, CONFIG_LS1012A should be CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be wrongly called to disable all dwc3 USB nodes on LS1012A, which cause Linux USB function stop working at all. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-08-29armv8/ls1088a: configure PMU's PCTBENR to enable WDTZhang Ying-22455
The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2017-08-29 LS1088A_QSPI: SECURE_BOOT: Images validationPrabhakar Kushwaha
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase using esbc_validate command. Add images validation in default environment under mcinitcmd prior to MC initialization. Add header address for PPA to be validated during ESBC phase for LS1088A platform based on LAyerscape Chasis 3. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
2017-08-29ls1088ardb: Add SD Secure boot target supportSumit Garg
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-08-29armv8: fsl-layerscape: SPL size reductionPrabhakar Kushwaha
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Compile-off mp.c and libfdt.c in case of SPL build. 2. Keep MMU and DCACHE specific variable and functions under CONFIG_SYS_DCACHE_OFF macro. 3. Compile-off IFC specific funtion call "init_early_memctl_regs" in case of SPL build. Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-08-25ls1088ardb: Enable USB command RDB qspi-bootAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
2017-08-23armv8: ls1088aqds: Add SD boot support for ls1088qdsAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8: ls1088ardb: Add SD boot support for ls1088Ashish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar
This patch adds support RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8: ls1088aqds: Add support of LS1088AQDSAshish Kumar
This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8: ls1088ardb: Add support for LS1088ARDB platformAshish Kumar
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
2017-08-23armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar
The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications. LS1088A is compliant with the Layerscape Chassis Generation 3. Features summary: - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Cores are in 2 cluster of 4-cores each - Cache coherent interconnect (CCI-400) - One 64-bit DDR4 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
2017-08-23armv8: fsl-layerscape: Put SATA code under SATA configsAshish Kumar
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8: fsl-lsch3: Make CCN-504 related code conditionalAshish Kumar
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs from LSCH3 may have differnt interconnect like LS1088. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-08-23armv7: Consolidate registers space defination for CCI-400 busAshish Kumar
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination "FSL_SYS_HAS_CCI400" and removes register space definaton of CCI-400 bus from immap_ls102xa to fsl_immap, since same is defined there already "CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET is introduced in Kconfig Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 busAshish Kumar
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and moves existing register space definaton of CCI-400 bus from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3. "CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET is introduced in Kconfig Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-08-21armv8/fsl-layerscape: fdt Update kaslr_seed only if sec_firmware is availableRuchika Gupta
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-17board/ls2081ardb: Some updates like flash typeSantan Kumar
Patch makes below changes: -Update QSPI flash type As per updated board design, different QSPI flash is connected on boards, hence change QSPI flash type from Micron n25q512a device to spansion s25fs512s device in dts and config. -Update QIXIS_QMAP_MASK value from 0x07 to 0x70 -Update checkboard() display of boot source and board information -Correct DSPI flash config selection -Remove deprecated config : CONFIG_DISPLAY_BOARDINFO_LATE Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2017-08-17armv8: Correct register offset define.Ran Wang
For USB erratum A-009007, original patch write the wrong register on LS208xa, need to be correct according to PDM information update. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-08-17uboot: Kconfig: add ERRATUM config to Kconfig for solve compile issue.yinbo.zhu
add erratum config to Kconfig and instead of config.h's config for solve ls2080rdb compiling issue Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-08-17armv8: Correct errata related patch defect.Ran Wang
Let patch code apply correct SoC. 1.A009007 2.A008997 3.A009798 4.A009008 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-08-17arm: Fix USB errata reilated patches issue.Ran Wang
1.Miss definition in Kconfig. 2.Compile switch should be CONFIG_ARCH_LSxxx. 3.Miss some register define. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-009008Suresh Gupta
USB High Speed (HS) EYE Height Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-009007Suresh Gupta
USB3PHY Observing Intermittent Failure in Rx This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-008997Suresh Gupta
USB3 LFPS Peak-Peak Differential Output Voltage Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-009798Ran Wang
USB High Speed Squelch Threshold Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
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