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This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.
Add esbh_halt() after the reset to make sure execution stops.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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The fsl-mc node has been moved under /soc, so update
the path references accordingly. Backwards compatibility
is retained for /fsl-mc.
Delete backwards compatibility for the completely obsolete
/fsl,dprc@0.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
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For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt. Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
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After power cycle of a K2G EVM dhcp fails due to a auto-negotiation
timeout. This commit increases the timeout to fix the issue.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Return i2c mux to the default channel after accessing retimer.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.
Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe
Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).
The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded. In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.
Signed-off-by: Tom Rini <trini@konsulko.com>
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When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case change things so that we
only build the right objects for SPL or non-SPL
Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
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After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.
This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.
We could maybe in the future map U-boot environment variables to EFI variables
here.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The hikey runs with dcache disabled today. There really should be no reason
not to use caches on AArch64, so let's add MMU definitions and enable the
dcache.
Signed-off-by: Alexander Graf <agraf@suse.de>
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There's no good excuse for running with caches disabled on AArch64,
so let's just move the vexpress64 target to enable the MMU and run
with caches on.
Signed-off-by: Alexander Graf <agraf@suse.de>
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The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.
Signed-off-by: Alexander Graf <agraf@suse.de>
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Reboot mode garbage is found on cold reset and might be seen as valid on the
next warm reset, thus it has to be cleared on cold reset.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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Some power on reasons are not desirable (e.g. too short press on the power
button), battery plug. Thus, power off the device when one of those occurs.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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USB ID pin pull-up indicates factory (fastboot) cable detection.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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This adds support for the omap4 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition or fastboot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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This adds support for the MUSB USB dual-role controller in peripheral mode,
with configuration options for the fastboot USB gadget.
At this point, flashing the internal eMMC is support.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.
It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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Boards using the TWL6030 regulator may not all use the LDOs the same way.
Some might also not use MMC1 at all, so VMMC would't have to be enabled.
This delegates TWL6030 MMC power initializations to board-specific functions,
that may still call twl6030_power_mmc_init for the default behavior.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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Reboot mode garbage is found on cold reset and might be seen as valid on the
next warm reset, thus it has to be cleared on cold reset.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
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There is no need to set the reboot mode to a particular value prior to reboot,
since valid values will have been caught and cleared earlier.
In addition, this breaks the reboot-bootloader fastboot call, by overriding the
required value for fastboot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
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All the mux configurations needs to be done as part of the IODelay
sequence to avoid glitch. Adding all the mux configuration, MANUAL/VIRTUAL
mode configuration as needed for DRA72-evm.
Also update the mux for SD card detect on DRA74-evm.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Updating the memory banks properly so that DT is populated accordingly.
And updating this only after DDR is properly detected by eeprom, so that
git bisect is still maintained.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory
chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the
same.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Enable EEPROM support for DRA74-evm.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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DRA7 EVM revH and later EVMs have EEPROM populated that can contain board
description information such as name, revision, DDR definition, etc. Adding
support for this EEPROM format.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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There are certain EMIF timing failures seen on the some x15 boards. Updating
the EMIF settings to get rid of these timing failures.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.
Tested on the Logic PD Torpedo + Wireless.
I only changed a handful of devices that used the same syntax as the Logic
board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods
and Alexander Graf.
Signed-off-by: Adam Ford <aford173@gmail.com>
V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c
V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c
V4: Fix subject heading
V3: Remove reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.
V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.
This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.
For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.
The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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