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Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.
Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
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Select MSR instructions via Kconfig instead of xparameters.h.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Toolchain can use some flags by default based on cpu version.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Remove autogenerated config.mk and select CPU options via Kconfig.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
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We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT
flag in global data after allocating memory using mem_malloc_init.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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These functions are part of the Linux 4.6 sync. They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.
Signed-off-by: Scott Wood <oss@buserror.net>
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nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Signed-off-by: Scott Wood <oss@buserror.net>
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QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should
be used for USB 3 & 2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.
Signed-off-by: York Sun <york.sun@nxp.com>
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LS102A ref manual dictates that ICID have to be written to the MSB
of the ICID register, not to the LSB.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
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This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.
Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.
Right now to give a default watchdog behaviour "Device reset" is
being selected.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
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This just fixes alignment for better readability.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Currently omap_vcores is wrongly assigned a default value of
beagle_x15_volts. Hence populating a new structure for am572x-idk
and assigning it to omap_vcores in the vcores_init function.
Fixes: c020d355c45ed40fe12a ("board: ti: am57xx: Add support for am572x idk in SPL")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
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The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.
Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.
Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros <rogerq@ti.com>
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Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request
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P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B
port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion
headers.
Currently, due to U-Boot's level of support for Tegra186, the only
features supported by U-Boot are the console UART and the on-board eMMC.
Additional features will be added over time.
U-Boot has so far been tested by replacing the kernel image on the device
with a U-Boot binary. It is anticipated that U-Boot will eventually
replace the CCPLEX bootloader binary, as on previous chips. This hasn't
yet been tested.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This patch reset the ethernet controller for ap143 board
Signed-off-by: Wills Wang <wills.wang@live.com>
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This patch enable network function for ap121 board.
Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
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Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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As the old ethernet PHY is not available any more, the x600 board has
been redesigned with the Micrel KSZ9031 PHY. This patch adds support
to autodetect the PHY and configure the Micrel PHY correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
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Enable ACPI table generation by creating a DSDT table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add minimal dts support for AM335x-ICEv2 board
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
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In order to enable cpsw on AM335x ICEv2 board, the following needs to be done:
1)There are few on board jumper settings which gives a choice between
cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting
this, there are few GPIOs which control these muxes that needs to be held high.
2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected
via I2C. This needs to properly programmed and locked for PHY operation.
And PHY needs to be reset before before being used, which is also held by
a GPIO.
3) RMII mode needs to be selected.
[1] http://www.ti.com/lit/zip/tidr336
[2] http://www.ti.com/lit/ds/symlink/cdce913.pdf
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125),
capable of running at 400MHz. Adding this specific DDR configuration
details running at 400MHz.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add necessary pinmux support for AM335x ICEv2 board.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Similar to other TI's AM335x platforms, AM335x ICEv2 also has an
eeprom populated for its unique identification. Adding this info
so that AM335x ICEv2 specific initialization can be done.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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