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path: root/cpu/mpc86xx/interrupts.c
AgeCommit message (Collapse)Author
2007-08-10cpu/86xx fixes.Jon Loeliger
Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-01Fix build errors and warnings / code cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-03-22Set Rev 2.x 86xx PIC in mixed mode.Haiying Wang
Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang <haiying.wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-08-22General indent and whitespace cleanups.Jon Loeliger
2006-05-31Review cleanups.Jon Loeliger
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-04-27Cleanup whitespaces and style issues.Jon Loeliger
Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft.
2006-04-26Initial support for MPC8641 HPCN board.Jon Loeliger