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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.
This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.
Lot's of other macros are good candidates to be consolidated this way
in the future.
Signed-off-by: Stefan Roese <sr@denx.de>
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platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.
this consequently eliminates CONFIG_ADD_RAM_INFO.
Thanks to Stefan for the hint.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better
support non default, boardspecific DDR(2) controller configuration.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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- Show on the Status LEDs, some States of the board.
- Get the MAC addresses from the EEProm
- use PREBOOT
- use the CF on the board.
- check the U-Boot image in the Flash with a SHA1
checksum.
- use dynamic TLB entries generation for the SDRAM
Signed-off-by: Heiko Schocher <hs@denx.de>
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Now program_tlb() allows to program a TLB (or multiple) with
different virtual and physical addresses. With this change, now one
physical region (e.g. SDRAM) can be mapped 2 times, once with caches
diabled and once with caches enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
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Add config option for 180 degree advance clock control as needed
for the AMCC Luan eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
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Additional RAM information is now printed upon powerup, like
DDR2 frequency and CAS latency.
Signed-off-by: Stefan Roese <sr@denx.de>
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Fix a bug in the auto calibration routine. This driver now runs
more reliable with the tested modules. It's also tested with
167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.
Please note, that still some problems are left with some memory
configurations. See the driver for more details.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:
- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)
This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
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