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path: root/drivers/ddr/marvell
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2016-02-06Use correct spelling of "U-Boot"Bin Meng
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-01-14mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter
This should make it clear that this symbol is meant to be defined by board headers. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14axp: Fix debugging support in DDR3 write levelingPhil Sutter
If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing. In addition to that, get rid of debug output printing non-existent counter variable. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14arm: mvebu: Make ECC support configurable on Armada XPStefan Roese
Currently, ECC support is enabled for all Armada XP boards. So the DDR3 driver tries to configure the controller with ECC support, even on boards without ECC. This patch makes this ECC optional which now can be configured on a board-per-board basis. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
2016-01-14arm: mvebu: ddr: Fix compilation warningStefan Roese
gcc 5.1 generates this new warning (for Armada 38x platforms): drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result': drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument] memcpy(result, training_result, sizeof(result)); ^ drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) ^ Since this functions is not referenced anywhere, lets just remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach
SAR1_CPU_CORE_MASK was wrong, probably copy/paste from another architecture. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2015-11-17arm: mvebu: a38x: Remove unsupported topologiesKevin Smith
A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-09-11bitops: introduce BIT() definitionHeiko Schocher
introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2015-08-17arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese
This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese
This is tested on the DB-MV784MP-GP eval board. To really enable ECC support on this board the I2C EEPROM needs to get changed. As it saves the enabling of ECC support internally. For this the following commands can be used to enable ECC support on this board: Its recommended for first save (print) the value(s) in this EEPROM address: => i2c md 4e 0.1 2 0000: 05 00 .. To enable ECC support you need to set bit 1 in the 2nd byte: Marvell>> i2c mw 4e 1.1 02 Marvell>> i2c md 4e 0.1 2 0000: 05 02 .. To disable ECC support again, please use this command: Marvell>> i2c mw 4e 1.1 00 Marvell>> i2c md 4e 0.1 2 0000: 05 00 .. On other AXP boards, simply plugging an ECC DIMM should be enough to enable ECC support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-23arm: mvebu: a38x: Use correct PEX register access macrosStefan Roese
Remove the incorrect PEX macros from the DDR header. And insert the correct ones in ctrl_pex.h instead. Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdrStefan Roese
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directoryStefan Roese
With the upcoming addition of the Armada 38x DDR support, which is not compatible to the Armada XP DDR init code, we need to introduce a new directory infrastructure. To support multiple Marvell DDR controller. This will be the new structure: drivers/ddr/marvell/axp Supporting Armada XP (AXP) devices (and perhaps Armada 370) drivers/ddr/marvell/a38x Supporting Armada 38x devices (and perhaps Armada 39x) Signed-off-by: Stefan Roese <sr@denx.de>