u-boot - NXP/Freescale LSDK U-boot tree with Scalys patches

Age	Commit message (Collapse)	Author
2013-11-25	Driver/DDR: Update DDR driver to allow non-zero base address	York Sun
	The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25	powerpc/mpc8xxx: Extend DDR registers' fields	York Sun
	Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25	Driver/DDR: Add Freescale DDR driver for ARM	York Sun
	Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	York Sun
	Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25	Driver/DDR: Moving Freescale DDR driver to a common driver	York Sun
	Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>