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Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC mode per command.
- Handle NAND_CMD_READOOB seperate. Make sure column and sector
size is correctly set up, while disabling ECC.
- Now, the OOB data end up at the beginning of the buffer. Remove
the special handling of OOB (spareonly).
Especially bad block scans benefit from this change. On a 512MiB
SLC NAND device, the bad block scan took 1.5s less than before.
Signed-off-by: Stefan Agner <stefan@agner.ch>
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Allow bit flips in a empty page up to half of the recoverable
bits (strength / 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
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Since we do not support sub-page writes anyway, reading the page
back to the controller on SEQIN command is not required. Remove
the page read on SEQIN.
However, the column/page values relevant to the SEQIN command, hence
set the column/row address on SEQIN command.
Signed-off-by: Stefan Agner <stefan@agner.ch>
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To improve performance we remember the current page in the buffer
and avoid reading it twice. This implicit page cache increases
complexity while does not increase performance in real world cases.
This patch removes that feature.
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
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Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: Marek Vasut <marex@denx.de>
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Calculate ecc strength according oobsize, but not hardcoded
which is not aligned with kernel driver
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <b37916@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
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Freeing allocated memory to priv before returning
from the function
Signed-off-by: Raghav Dogra <raghav@freescale.com>
[scottwood: removed unnecessary cast]
Signed-off-by: Scott Wood <scottwood@freescale.com>
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On systems with caches enabled, NAND I/O may need to flush/invalidate
the cache during read/write operations. For this to work correctly, all
buffers must be cache-aligned. Fix nand_verify*() to allocate aligned
buffers.
This prevents cache alignment warnings from being spewed when using
U-Boot to write an updated version of itself to flash on NVIDIA Tegra
Seaboard (after perturbation of stack/data layout in current
u-boot-dm/next branch).
I have validatd (executed) nand_verify(), but I don't think I've executed
nand_verify_page_oob(); testing of that would be useful.
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Fixes: 59b5a2ad83df ("nand: Add verification functions")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
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This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
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IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
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IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers. Fix the resulting array overflow.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Josh Wu <josh.wu@atmel.com>
CC: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
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Testing showed, that commands like STATUS made the buffer dirty
when executed with NFC_SECSZ set to the page size. It looks
like the controller transfers bogus data when this register
is configured. When setting it to 0, the buffer does not get
altered while the status command still seems to work flawless.
Signed-off-by: Stefan Agner <stefan@agner.ch>
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The driver tries to re-use the page buffer by storing the page
number of the current page in the buffer. The page is only read
if the requested page number is not currently in the buffer. When
a block is erased, the page number is marked as invalid if the
erased page equals the one currently in the cache. However, since
a erase block consists of multiple pages, also other page numbers
could be affected.
The commands to reproduce this issue (on a written page):
> nand dump 0x800
> nand erase 0x0 0x20000
> nand dump 0x800
The second nand dump command returns the data from the buffer,
while in fact the page is erased (0xff).
Avoid the hassle to calculate whether the page is affected or not,
but set the page buffer unconditionally to invalid instead.
Signed-off-by: Stefan Agner <stefan@agner.ch>
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This command is only enabled by one board, complicates the NAND code,
and doesn't appear to have been functioning properly for several
years. If there are no bad blocks in the NAND region being written
nand_write_skip_bad() will take the shortcut of calling nand_write()
which bypasses the special yaffs handling. This causes invalid YAFFS
data to be written. See
http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for
an example and a potential workaround.
U-Boot still retains the ability to mount and access YAFFS partitions
via CONFIG_YAFFS2.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
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Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies
NAND contents against an arbitrarily sized buffer using ECC while
nand_verify_page_oob() verifies a NAND page's contents and OOB.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
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There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
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There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
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The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
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Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.
This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:
#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.
Signed-off-by: Michal Sojka <sojka@merica.cz>
Acked-by: Stefan Roese <sr@denx.de>
Tested-by: Michal Vokáč <michal.vokac@comap.cz>
Cc: Tom Rini <trini@ti.com>
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Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.
It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:
[1] It is impossible to share CONFIG options across the images.
If you change the configuration of Main image, you often have to
adjust some SPL configurations correspondingly. Currently, we
cannot handle the dependencies between them. It means one of the
biggest advantages of Kconfig is lost.
[2] It is too painful to change both ".config" and "spl/.config".
Sunxi guys started to work around this problem by creating a new
configuration target. Commit cbdd9a9737cc (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.) added
"make *_felconfig" to enable CONFIG_SPL_FEL on both images.
Changing the configuration of multiple images in one command is a
generic demand. The current implementation cannot propose any
good solution about this.
[3] Kconfig files are getting ugly and difficult to understand.
Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.
[4] The build system got more complicated than it should be.
To adjust Linux-originated Kconfig to U-Boot, the helper script
"scripts/multiconfig.sh" was introduced. Writing a complicated
text processor is a shell script sometimes caused problems.
Now I believe the "single .config" will serve us better. With it,
all the problems above would go away. Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much. Anyway, this is what we do now in
scripts/Makefile.spl.
I admit my mistake with my apology and this commit switches to the
single .config configuration.
It is not so difficult to do that:
- Remove unnecessary processings from scripts/multiconfig.sh
This file will remain for a while to support the current defconfig
format. It will be removed after more cleanups are done.
- Adjust some makefiles and Kconfigs
- Add some entries to include/config_uncmd_spl.h and the new file
scripts/Makefile.uncmd_spl. Some CONFIG options that are not
supported on SPL must be disabled because one .config is shared
between SPL and U-Boot proper going forward. I know this is not
a beautiful solution and I think we can do better, but let's see
how much we will have to describe them.
- update doc/README.kconfig
More cleaning up patches will follow this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The patch c316f577b4b72d1a1aeb559e9b3fad20808f1ffd breaks
siemens boards because prefetch mode is not enabled.
I assume it breaks other boards as well that don't use
prefetch.
This patch sets read_buf to nand_read_buf if
NAND_OMAP_GPMC_PREFETCH is not defined.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
CC: Daniel Mack <zonque@gmail.com>
CC: Guido Martínez <guido@vanguardiasur.com.ar>
CC: Tom Rini <trini@ti.com>
CC: Heiko Schocher <hs@denx.de>
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As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
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These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
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Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.
The current implementation has two limitations:
a) it only works in 8-bit mode
b) it only supports read access
Both is easily fixable by someone who has hardware to implement it.
Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.
Tested on AM335x hardware.
Tested-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar>
Signed-off-by: Daniel Mack <zonque@gmail.com>
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini <trini@ti.com>
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Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.
It violates the intention of NAND_SKIP_BBTSCAN.
Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.
Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub. We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
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Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning)
broke NAND_BBT_USE_FLASH feature.
Its git-log claimed that it reinstated the change as by commit
fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".
It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.
Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rostislav Lisovy <lisovy@merica.cz>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
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Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14),
the "nand scrub" command has not been working.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
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"err" was an unsigned variable, causing negative error codes to turn
into positive values, which are interpreted as an amount of succesfully
corrected bitflips (and thus not an error).
In particular, this resulted in that if the elm reports uncorrectable
errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Stefan Roese <sr@denx.de>
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'eccstat' array elements might be used uninitialized
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.
Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:
Without NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.947 seconds, 2947 ticks
With NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.795 seconds, 2795 ticks
So an increase of approx. 5%.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
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Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
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This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.
Patch has been tested on a Colibri VF61 module.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc. Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices. The device parameters detected
during nand_scan_ident() are more trustworthy.
This commit sets some hardware registers to mtd->pagesize,
mtd->oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
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Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().
CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux. Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
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Commit ff94bc40af3481d47546595ba73c136de6af6929
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde
("NAND: Scan bad blocks lazily.").
Reinstate the change as by commit
fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea
("nand: reinstate lazy bad block scanning")
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Heiko Schocher <hs@denx.de>
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U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
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As in SAMA5D4 SoC, the gf table in ROM code can not be seen.
So, when we try to use PMECC, we need to build it when do
initialization.
Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it
is defined we will build gf table runtime.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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device ready pin is signalling that the device is ready on state 1
not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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erase one nand block in spl code. keep it simple, as size matters
This is used on the upcoming taurus spl support.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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using this driver in SPL code with CONFIG_SPL_NAND_ECC
configured leads in an compileerror. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Add ECC geometry for NAND which has 2048b pagesize and 112b OOB
size. This is for example Macronix MX30LF2G28AB chip.
Signed-off-by: Marek Vasut <marex@denx.de>
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- make omap_spl_dev_ready static
- make omap_reverse_list static, move to under CONFIG_NAND_OMAP_ELM
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@ti.com>
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