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2009-10-13SMC911X: Add chip auto detectionOlof Johansson
Refactor the smc911x driver to allow for detecting when the chip is missing. I.e. the detect_chip() function is called earlier and will abort gracefully when the Chip ID read returns all 1's. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-13OMAP3 MMC: Fix warning dereferencing type-punned pointerDirk Behme
Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Steve Sakoman <sakoman@gmail.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-12Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk
2009-10-12Leave x86emu op code tables in default sectionEd Swarthout
Forcing the tables into got2 caused extra relocation when using -mrelocatable. This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Jin Zhengxiong <Jason.Jin@freescale.com>
2009-10-11Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an ↵Luigi 'Comio' Mantellini
arbitrary number of mii buses. This feature is useful when your board uses different mii buses for different phys and all (or a part) of these buses are implemented via bit-banging mode. The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver CONFIG_BITBANGMII_MULTI - Enable the multi bus support If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs to define at least the following macros: MII_INIT - Generic code to enable the MII bus (optional) MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) MDIO_ACTIVE - Activate the MDIO pin as out pin MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin MDIO_READ - Read the MDIO pin MDIO(v) - Write v on the MDIO pin MDC_DECLARE - Declaration needed to access to the MDC pin (optional) MDC(v) - Write v on the MDC pin The previous macros make the driver compatible with the previous version (that didn't support the multi-bus). When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill the bb_miiphy_buses[] array with a record for each required bus and declare the bb_miiphy_buses_num variable with the number of mii buses. The record (struct bb_miiphy_bus) has the following fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name int (*init)() - Initialization function called at startup time (just before the Ethernet initialization) int (*mdio_active)() - Activate the MDIO pin as output int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin int (*set_mdio)() - Write the MDIO pin int (*get_mdio)() - Read the MDIO pin int (*set_mdc)() - Write the MDC pin int (*delay)() - Delay function void *priv - Private data used by board specific code The board code will look like: struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... }, { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... }, ... int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-08Merge branch 'reloc'Wolfgang Denk
2009-10-07ppc_4xx: Apply new HW register namesNiklaus Giger
Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-05net: kirkwood_egiga.c: fixed build warningPrafulla Wadaskar
if link up detection code is disabled through config option, it gives build warning. This patch fixes the same Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-05Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI APIBen Warren
All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-05net: phy: mv88e61xx.c : fixed build warningPrafulla Wadaskar
following build warning was observed mv88e61xx.c: In function ‘mv88e61xx_busychk’: mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules This patch fixes the same Patch tested for rd6281a board build Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-05net: Fix problem with 405EZ ethernet interruptJames Clough
On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the UIC. We need to acknowledge the RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. This problem was introduced with commit d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines] Signed-off-by: James Clough <james@rtetc.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-03Conditionally perform common relocation fixupsPeter Tyser
Add #ifdefs where necessary to not perform relocation fixups. This allows boards/architectures which support relocation to trim a decent chunk of code. Note that this patch doesn't add #ifdefs to architecture-specific code which does not support relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03fpga: Remove relocation fixupsPeter Tyser
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03tsec: Remove PHY command relocation fixupsPeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-30Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2009-09-30Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk
2009-09-30Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk
2009-09-30ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPLKumar Gala
Don't include get_law_entry as part of the NAND_SPL build since the code isnt used. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-28NAND: davinci: Fix warnings when 4-bit ECC not usedScott Wood
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support" applied when I pushed the tree last merge window, and missed these fixes which were in v3 of that patch. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-28fsl_i2c: Do not generate STOP after read.Joakim Tjernlund
__i2c_read always ends with a STOP condition thereby releasing the bus. It is cleaner to do the STOP magic in i2c_read(), like i2c_write() does. This may also help future multimaster systems which wants to hold on to the bus until all transactions are finished. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-09-28fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSRJoakim Tjernlund
The latest AN2919 has changed the way FDR/DFSR should be calculated. Update the driver according to spec. However, Condition 2 is not accounted for as it is not clear how to do so. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
2009-09-28fsl_i2c: Add CONFIG_FSL_I2C_CUSTOM_{DFSR/FDR}Joakim Tjernlund
Some boards need a higher DFSR value than the spec currently recommends so give these boards the means to define there own. For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-09-28fsl_i2c: Wait for STOP condition to propagateJoakim Tjernlund
After issuing a STOP one must wait until the STOP has completed on the bus before doing something new to the controller. Also add an extra read of SR as the manual mentions doing that is a good idea. Remove surplus write of CR just before a write, isn't required and could potentially disturb the I2C bus. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-09-25net: uec: Fix uccf.h and uec.h headers to include headers they depend onAnton Vorontsov
Headers should include headers containing prototypes and defines they depend on, don't assume that they're included by somebody else. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYsAnton Vorontsov
This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-24Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk
2009-09-24ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala
There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala
On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24ppc/85xx: Clean up p1_p2_rdb PCI setupKumar Gala
General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-23rtc/ds1337.c: Allow to set TCR registerWerner Pfister
This is needed to correctly start the charging of an attached capacitor or battery. Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de> Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-09-22mpc512x. Micron nand flash needs a reset before a read command is issued.Paul Gibson
Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
2009-09-16ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk
2009-09-15Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk
2009-09-14sk98lin: fix compile warningsWolfgang Denk
Fix warnings: skge.c: In function 'BoardInitMem': skge.c:1389: warning: dereferencing type-punned pointer will break strict-aliasing rules skge.c:1390: warning: dereferencing type-punned pointer will break strict-aliasing rules skge.c:1391: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c: In function 'SkGePortCheckUpXmac': skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules skrlmt.c: In function 'SkRlmtInit': skrlmt.c:661: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacPromiscMode': skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacHashing': skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacFlushTxFifo': skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacFlushRxFifo': skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkXmInitPauseMd': skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkXmOverflowStatus': skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Ben Warren <biggerbadderben@gmail.com>
2009-09-14drivers/net/natsemi.c: fix compile warningWolfgang Denk
Fix warning: natsemi.c:757: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Ben Warren <biggerbadderben@gmail.com>
2009-09-14net: emaclite: Cleanup license to be GPL compatibleMichal Simek
Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14net: Remove old Xilinx Emac driverMichal Simek
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-11ppc4xx: Big cleanup of PPC4xx definesStefan Roese
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-08fsl: add register read-back to set_law()Timur Tabi
After programming a new LAW, we should read-back the LAWAR register so that we sync the writes. Otherwise, code that attempts to use the new LAW-mapped memory might fail right away. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-06fsl_i2c: increase I2C timeout values and make them configurableTimur Tabi
The value of I2C_TIMEOUT in fsl_i2c.c has several problems. First, it is defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes no sense to derive it from a clock rate. Second, the current value (250) is too low for some boards, so it needs to be increased. Third, the timeout necessary for multiple-master arbitration is larger than the timeout for basic read/write operations, so we shouldn't have a single constant for both timeouts. Finally, it would be nice if we could override these values on a per-board basis. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> Tested-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-04mxc_nand: Remove Freescale's "All Rights Reserved."Scott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-04License cleanup: remove unintended "All Rights Reserved" notices.Wolfgang Denk
Some files included my old standerd file header which had a "All Rights Reserved" part. As this has never been my intention, I remove these lines to make the files compatible with GPL v.2 and later. Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-04Use different PBA value for E1000 PCI and PCIe cardsRoy Zang
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: André Schwarz <andre.schwarz@matrix-vision.de>
2009-09-04Misc ds1722 fixupsGraeme Russ
This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD on 18th May 2008 as part of a general i386 / sc520 fixup which was never applied Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04Misc ti_pci1410a fixupsGraeme Russ
Removed do_pinit() - now declared in cmd_pcmcia.c Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other PCMCIA drivers signed/unsigned type fixups Added semi-colon after default: label as required by newer gcc The only board that appears to use this driver is the sc520_spunk which is very old and very likely very broken anyway. I do not have one to test whether this patch breaks anything functionaly, I have can only check that it compiles without warning or error Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04Misc SATA fixupsGraeme Russ
Cast first parameter to sata_cpy() In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(), ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in include/libata.h which is included in ata.h which is included by all files which include ata_piix.h (only ata_piix.c) so these definitions are supurflous to (and conlict with) this in libata.h. Interestingly, my compiler complains about ata_id_u64 already being defined, but not ata_id_u32 ata_dump_id() is defined in include/libata.h and should not be static (maybe should even use ata_dump_id() in libata.c Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-08-28driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal
fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal
P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Added P1020 Processor Support.Poonam Aggrwal
P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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