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The stm_is_locked_sr() function is picked from Linux kernel. For reason
unknown, the 64bit data types used by the function and present in Linux
were replaced with 32bit unsigned ones, which causes trouble.
The testcase performed was done using ST M25P80 chip.
The command used was:
=> sf protect unlock 0 0x10000
The call chain starts in stm_unlock(), which calls stm_is_locked_sr()
with negative ofs argument. This works fine in Linux, where the "ofs"
is loff_t, which is signed long long, while this fails in U-Boot, where
"ofs" is u32 (unsigned int). Because of this signedness problem, the
expression past the return statement to be incorrectly evaluated to 1,
which in turn propagates back to stm_unlock() and results in -EINVAL.
The correction is very simple, just use the correctly sized data types
with correct signedness in the function to make it work as intended.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
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TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is
not strictly correct, as it gives a build warning when fdt_addr_t is u64.
So, use map_physmem for a proper typecasts.
This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address
instead of a pointer for the uart base")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
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CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER
to guard the drivers/pinctrl/uniphier directory.
The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it
into CONFIG_PINCTRL_UNIPHIER.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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While IECTRL is disabled, input signals are pulled-down internally.
If pin-muxing is set up first, glitch signals (Low to High transition)
might be input to hardware blocks.
Bad case scenario:
[1] The hardware block is already running before pinctrl is handled.
(the reset is de-asserted by default or by a firmware, for example)
[2] The pin-muxing is set up. The input signals to hardware block
are pulled-down by the chip-internal biasing.
[3] The pins are input-enabled. The signals from the board reach the
hardware block.
Actually, one invalid character is input to the UART blocks for such
SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the
power on reset.
To avoid such problems, pins should be input-enabled before muxing.
[ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ]
Fixes: 5dc626f83619 ("pinctrl: uniphier: add UniPhier pinctrl core support")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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For the case where an external VBUS is used, we should enable the external
VBUS comparator in the driver. This would prevent an unnecessary overcurrent
error which would then disable the host port.
The overcurrent condition was happening on the SoCFPGA Cyclone5 devkit, thus
USB was not working on the devkit. This patch fixes that problem.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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In case when usb_composite_register() failed once (for whatever reason),
it will fail further even if all conditions are correct. Example:
=> fastboot 2
Invalid Controller Index
couldn't find an available UDC
g_dnl_register: failed!, error: -19
exit not allowed from main input shell.
=> fastboot 0
g_dnl_register: failed!, error: -22
exit not allowed from main input shell.
Despite that 0 is correct index for USB controller, "fastboot 0" command
will fail, because "composite" structure wasn't cleared properly on
previous fail (on "fastboot 2" command).
This patch fixes that erroneous behavior, allowing us to use composite
even after previous failure.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
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This reverts commit d9a3bec682f9756621615f4306718a356a3230e3.
While this is a correct change to do long term it unfortunately breaks a
number of platforms that are using pdata and not named struct members so
they are getting all of their data after 'base' incorrect.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Add a driver for the on-chip SD/eMMC host controller used by
UniPhier SoC family.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This GPIO controller device is used on UniPhier SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
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In commit <a058052c358c> [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.
To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Fix the following warning on aarch64 introduced by using p2v/v2p
functions in the code:
In file included from ./arch/arm/include/asm/byteorder.h:29:0,
from include/compiler.h:125,
from include/image.h:19,
from include/common.h:88,
from drivers/usb/host/ehci-hcd.c:10:
drivers/usb/host/ehci-hcd.c: In function ‘ehci_td_buffer’:
drivers/usb/host/ehci-hcd.c:250:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
^
include/linux/byteorder/little_endian.h:34:51: note: in definition of macro ‘__cpu_to_le32’
#define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
^
drivers/usb/host/ehci-hcd.c:250:24: note: in expansion of macro ‘cpu_to_hc32’
td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
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Fix the following compiler warnings when DEBUG is on.
warning: 'bar_res' may be used uninitialized in this function.
drivers/pci/pci_auto.c:101:21:
if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
^
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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When an error number is provided we should use it, not change it. This fixes
the SPI and SPI flash tests.
One of these is long-standing. The other seems to have been introduced by
commit 1e90d9fd (sf: Move read_id code to sf_ops).
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 1e90d9fd (sf: Move read_id code to sf_ops)
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
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We must not free data that is managed by driver mode. Remove this line,
which is a hangover from the pre-driver-model code.
This fixes a problem where 'sf probe' crashes U-Boot if the backing file
for the SPI flash cannot be found.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Add a little more debugging to help when things go wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
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Add support for the early timer so we can use tracing with sandbox again.
Signed-off-by: Simon Glass <sjg@chromium.org>
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In some cases the timer must be accessible before driver model is active.
Examples include when using CONFIG_TRACE to trace U-Boot's execution before
driver model is set up. Enable this option to use an early timer. These
functions must be supported by your timer driver: timer_early_get_count()
and timer_early_get_rate().
Signed-off-by: Simon Glass <sjg@chromium.org>
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A few of the functions in the timer uclass are not marked with 'notrace'. Fix
this so that tracing can be used with CONFIG_TRACE.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Enabling this driver requires some DT changes.
Adding DCC to root or main bus:
dcc: dcc {
compatible = "arm,dcc";
u-boot,dm-pre-reloc;
};
Extend alias list to link DCC:
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
Change stdout-path to point to dcc port.
stdout-path = "serial2:115200n8";
Also add support for debug uart to help with early debug.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add the following functions:
tps65218_reg_read() for accessing redisters
tps65218_toggle_fseal() for toggling the fseal bit
tps65218_lock_fsea() for locking the fseal bit to 1
Add the following defines:
All status register bits
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Building pci_rom.c with my toolchain complains about may be used uninitialized
rom varaible:
---8<---
+drivers/pci/pci_rom.c:269:25: note: 'rom' was declared here
w+drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios':
w+drivers/pci/pci_rom.c:154:14: warning: 'rom' may be used uninitialized in this function [-Wmaybe-uninitialized]
--->8---
Fix this as done in 55616b86c745fcac5a791268ab8e7cba36965c0f the ram variable.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
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This patch adds support for stm32f7 family & stm32f746 board.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
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This patch adds support for stm32f7 family usart peripheral.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
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This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
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Fix the formatting in error messages, and demote one error message
to a warning, as it is only informational.
Signed-off-by: Steve Rae <srae@broadcom.com>
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The alignment and size were swapped, leading to malloc heap corruption.
On my system, this sometimes caused U-Boot to crash during or after
certain USB Ethernet operations.
Fixes: c8c2797c3810 ("dm: usb: eth: Support driver model with USB Ethernet")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This patch fixes situation when one would like to write large file into
medium with the file system (fat, ext4, etc).
This change sets file size limitation to the DFU internal buffer size.
Since u-boot is not supporting interrupts and seek on file systems, it
becomes challenging to store large file appropriately.
To reproduce this error - create large file (around 26 MiB) and sent it
to the target board.
Lets examine the flow of USB transactions:
0. DFU uses EP0 with 64B MPS [Max Packet Size]
1. Send file - OUT (PC->target) - dat_26MiB.img is sent with 4096 B transactions
2. Get status - OUT (PC->target) - wait for DFU_STATE_dfuDNLOAD_IDLE (0x05) sent
from target board - IN transaction
(target->PC)
3. The whole file content is sent to target - OUT (PC->target) with ZLP [Zero
Length Packet]
Now the interesting part starts:
4. OUT (PC->target) Setup transaction (request to share DFU state)
5. IN (target->PC) - reply the current DFU state
- In the UDC driver the req->completion (with dfu_flush) is called
after successful IN transfer.
- The dfu_flush() (called from req->completion callback) saves the
whole file at once (u-boot doesn't support seek on fs).
Such operation takes considerable time. When the file
is large - e.g. 26MiB - this time may be more than 5 seconds.
6. OUT (PC->target) - ZLP, is send in the same time when dfu_flush()
writes data to eMMC memory.
The dfu-util application has hard coded timeout on USB transaction
completion set to 5 seconds (it uses libusb calls).
When the file to store is large (e.g. 26 MiB) the time needed to write it
may excess the dfu-util timeout and following error message will be displayed:
"unable to read DFU status" on the HOST PC console.
This change is supposed to leverage DFU's part responsible for storing files
on file systems. Other DFU operations - i.e. raw/partition write to NAND and
eMMC should work as before.
The only functional change is the error reporting. When dfu_flush() fails
the u-boot prompt will exit with error information and dfu-util application
exits afterwards as well.
Test HW:
- Odroid XU3 (Exynos5433) - test with large file
- Trats (Exynos4210) - test for regression - eMMC, raw,
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reported-by: Alex Gdalevich <agdalevich@axion-biosystems.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Heiko Schocher <hs@denx.de>
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Add explicit cpu_to_be32()/be32_to_cpu() conversion to BE EHCI I/O
accessors to align them with their LE counterpart. No functional
change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
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If the USB EHCI is configured for little endian MMIO, make sure to
clear the USBMODE_BE flag from the USBMODE register.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
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Certain processor architectures, like MIPS, require that the USB
structures and transfer buffers are passed with their PA to the
USB controller. If VA is passed, the USB will not work. Add the
necessary virt_to_phys() calls into the USB EHCI code to make it
work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
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Some architectures, like MIPS, require remapping of the registers.
Add the map_physmem() call to handle it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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there are some code in qe.c not used for micro QE,
use "#ifdef CONFIG_QE" to mask them.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Use fdt32_to_cpu() to convert the data correctly for both endianness
platforms.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Not only powerpc/mpc85xx but also Freescale Layerscape platforms will
use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device
tree. So move the function to Fman driver code.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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The output ring needs to be invalidated before enqueuing the job to SEC.
While allocation of space to output ring, it should be taken care that the
size is cacheline size aligned inorder to prevent invalidating valid data.
The patch also correct the method of aligning end of structs while flushing caches
Since start = align(start_of_struct), it is incorrect to assign
end = align(start + struct_size). It should instead be,
end = align(start_of_struct + struct_size).
Signed-off-by: Saksham Jain <saksham@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Add support for phy 1-3.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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SY8106A is a PMIC which is used on the Allwinner
H3 Orange Pi Pc and Plus board. The VOUT1_SEL register is
implemented to set the default V-CPU voltage to 1200 mV.
This driver is required to ensure the SY8106A V-CPU
voltage is set to 1200 mV after a software reset. On cold
boot the default SY8106A output voltage is selected to be
1200 mV by a pair of resistors on the Orange Pi PC and Plus.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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In some case wordlen may not be set. Use SPI_DEFAULT_WORDLEN as default.
Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
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