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2017-12-19Grapeboard support addedvojo
2017-10-30driver: net: ldpaa_eth: Add PHY-less SGMII supportAshish Kumar
In case of PHY-less mode, there is no interaction with PHY so auto-neg etc is not required and link will have fixed attributes Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-10-30drivers: net: ldpaa_eth: Correct error handler for qbman_swp_acquire()Ashish Kumar
Correcting error handing for qbman_swp_acquire. The return value is zero is an error condition since number of buffer copied is zero meaning there are no free buffers for allocation. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kushwaha Prabhakar <prabhakar@freescale.com>
2017-10-17board: freescale: ls1012a: fix RGMII tx delay issueCalvin Johnson
Recently logic to enable RGMII tx delay was changed by below patch. "net: phy: realtek: fix enabling of the TX-delay for RTL8211F" Based on the patch, here we are enabling the tx delay again. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-13armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_IDAshish Kumar
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID PHY_INTERFACE_MODE_RGMII_TXID. These change where introduced in phy driver in commit titled "net: phy: realtek: fix enabling of the TX-delay for RTL8211F" Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-10-11configs: ls1012a: add pfe configuration for LS1012ACalvin Johnson
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11drivers: net: pfe_eth: provide pfe commandsCalvin Johnson
pfe_command provides command line support for several features that support pfe like starting or stopping the pfe, checking the health of the processor engines and checking status of different unit inside pfe. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11drivers: net: pfe_eth: LS1012A PFE driver introductionCalvin Johnson
This patch adds PFE driver into U-Boot. Following are the main driver files:- pfe.c: provides low level helper functions to initialize PFE internal processor engines and other hardware blocks. pfe_driver.c: provides probe functions, initialization functions and packet send and receive functions. pfe_eth.c: provides high level gemac, phy and mdio initialization functions. pfe_firmware.c: provides functions to load firmware into PFE internal processor engines. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
2017-10-11driver: fsl-mc: memset pointers after mallocPrabhakar Kushwaha
Memory allocated via malloc is not guaranteed to be zeroized. So explicitly use calloc instead of malloc. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-09-28QE: Set QE_IRAM_READY after uploading firmwareZhao Qiang
QE_IRAM_READY should be set only after successfully uploading the firmware. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-04pci: layerscape: Fixup iommu-map for LS208xABharat Bhushan
"pci: layerscape: Fixup device tree node for ls2088a" added support for LS208xA devices but fixing iommu-map property is missing. This patch adds support for fixing iommu-map. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-08-25spi: fsl_qspi: Add controller busy check before new spi operationSuresh Gupta
It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
2017-08-25PCI: layerscape: Make the pcie link up status judgement more specificBao Xiaowei
For some special reset times for longer pcie devices, in this case, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state. So add the link up status judgement mechanisms. Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
2017-08-23armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar
This patch adds support RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23driver: net: ldpaa: Update priv->phydev after free()Prabhakar Kushwaha
Even after memory free of phydev, priv is still pointing to the obsolete address. So update priv->phydev as NULL after memory free. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-08-23armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar
The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications. LS1088A is compliant with the Layerscape Chassis Generation 3. Features summary: - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Cores are in 2 cluster of 4-cores each - Cache coherent interconnect (CCI-400) - One 64-bit DDR4 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
2017-08-23net: phy: realtek: fix enabling of the TX-delay for RTL8211FMadalin Bucur
The old logic always enabled the TX-delay when the phy-mode was set to PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and disable it for PHY_INTERFACE_MODE_RGMII. Based on a similar change made in the Linux Realtek PHY driver by Martin Blumenstingl <martin.blumenstingl@googlemail.com>. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: York Sun <york.sun@nxp.com>
2017-08-23net: fman: add support RGMII_TXID to memacMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-17driver: net: fsl-mc: fsl_mc_ldpaa_exit exit earlier if dpl appliedSantan Kumar
In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied, it should return earlier without executing dpbp_exit() Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Acked-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
2017-08-16soc/fsl-layerscape: Update SVR number for LS2081A and LS2041ASantan Kumar
Update SVR as per the SOC document. -LS2081A: 0x870919 -> 0x870918 -LS2041A: 0x870915 -> 0x870914 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-08-08PCI: layerscape: Fix the bug assigning wrong address to LS2088A pcie cfg1 spaceHou Zhiqiang
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add LS2088A series SoC pcie support), which only updated cfg_res.start and did not update the .end field, this will make fdt_resource_size() getting wrong value when calculate the cfg1 space address. This patch is to fix the bug. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-08-08usb: xhci: Enable TT to support LS/FS devices behind a HS hubBin Meng
So far LS/FS devices directly attached to xHC root port can be successfully enumerated by xHCI driver, but if they are connected behind a hub, the enumeration process fails to address the device. It turns out xHCI driver still misses a part that in the device's input slot context, all Transaction Translator (TT) related fields are not programmed. The xHCI spec defines how to enable TT. Now LS/FS devices like USB keyboard/mouse can be enumerated behind a high speed hub. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci: Correct TT_SLOT and TT_PORT macrosBin Meng
These two macros really need a parameter to make them useful. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci: Implement update_hub_device() operationBin Meng
There is no way to know whether the attached device is a hub or not in advance before the device's descriptor is fetched. But once we know it's a high speed hub, per the xHCI spec, we need to tell xHC it's a hub device by initializing hub-related fields in the input slot context. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08dm: usb: Add a new USB controller operation 'update_hub_device'Bin Meng
For USB host controllers like xHC, its internal representation of hub needs to be updated after the hub descriptor is fetched. This adds a new op that does this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci: Program 'route string' in the input slot contextBin Meng
xHCI spec says: the values of the 'route string' field shall be initialized by the first 'Address Device' command issued to a device slot, and shall not be modified by any other command. So far U-Boot does not program this field, and it does not prevent SS device directly attached to root port, or HS device behind an HS hub, from working, due to the fact that 'route string' is used by the xHC to target SS packets. But in order to enumerate devices behind an SS hub, this field must be programmed. With this commit and along with previous commits, now SS & HS devices attached to a USB 3.0 hub can be enumerated by U-Boot. As usual, this new feature is only available when DM is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci: Change xhci_setup_addressable_virt_dev() signatureBin Meng
For future extension, change xhci_setup_addressable_virt_dev() signature to accept a pointer to 'struct usb_device', instead of its members slot_id & speed, as the struct already contains these two plus some other useful information of the device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: hub: Add a new API to test if a hub device is root hubBin Meng
Sometimes we need know if a given hub device is root hub or not. Add a new API to test this. This removes the xHCI driver's own version is_root_hub() and change to use the new API. While we are here, remove the unused/commented out get_usb_device() in the xHCI driver too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08usb: hub: Use 'struct usb_hub_device' as hub device's uclass_privBin Meng
Use USB hub device's dev->uclass_priv to point to 'usb_hub_device' so that with driver model usb_hub_reset() and usb_hub_allocate() are no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci-pci: Clean up the driver a little bitBin Meng
This cleans up the driver a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci-pci: Drop non-DM version of xhci-pci driverBin Meng
As there is no board that currently uses xhci-pci driver without DM USB, drop its support and leave only DM support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08usb: xhci: Convert CONFIG_USB_XHCI_PCI to KconfigBin Meng
Add CONFIG_USB_XHCI_PCI as a Kconfig option. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: ehci: Get rid of CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTSBin Meng
EHC reports supported maximum number of ports in the HCSPARAMS register, so it's unnecessary to use a hardcoded config option CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: xhci: Get rid of CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTSBin Meng
xHC reports supported maximum number of ports in the HCSPARAMS1 register, so it's unnecessary to use a hardcoded config option CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: xhci: Change MAX_HC_PORTS to 255Bin Meng
HCSPARAMS1:MaxPorts field specifies the maximum port number value, and its valid values are in the range of 1 to 255. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: hub: Change USB hub descriptor to match USB 3.0 hubsBin Meng
USB 3.0 hubs have a slightly different hub descriptor than USB 2.0 hubs, with a fixed (rather than variable length) size. Change the host controller drivers that access those last two fields (DeviceRemovable and PortPowerCtrlMask) to use the union. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: hub: Send correct wValue to get hub descriptor of a USB 3.0 hubBin Meng
Testing a USB 3.0 hub by connecting it to the xHCI port on Intel MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI reports a transfer event TRB with a completion code 6 which means 'Stall Error'. In fact super speed USB hub descriptor type is 0x2a, not 0x29. Sending correct SETUP packet to the hub makes it not stall anymore. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: xhci: Add input slot context in xhci_set_configuration()Bin Meng
A valid input slot context for a 'configure endpoint' command requires the 'Context Entries' field to be initialized to the index of the last valid endpoint context that is defined by the target configuration. We set up the 'Context Entries' field, but we forget to include the input slot context in the input control context 'Add Context flags' bitmap. So xHC will simply ignore input slot context and continue using its own which contains old information of the device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: xhci: Initialize scratchpad buffer array and scratchpad buffersBin Meng
The scratchpad buffer array is used to define the locations of statically allocated memory pages that are available for the private use of the xHC. The xHCI spec explicitly mentions that system software shall allocate the scratchpad buffers before placing the xHC in to Run mode (Run/Stop (R/S) = ‘1’), however U-Boot is missing this part. This causes xHC on Intel platform does not respond the very first 'enable slot' command that is given to xHC and the 'enable slot' command completion event TRB is never generated and xHC seems to hang forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: xhci: Correct command TRB 4th dword initializationBin Meng
In xhci_queue_command(), when the command is not 'reset endpoint', 'stop endpoint' or 'set TR dequeue pointer', endpoint ID should not be encoded in the TRB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-08-08usb: xhci: Remove incorrect comments for struct xhci_container_ctxBin Meng
There is no member called 'dma' in struct xhci_container_ctx. Remove the comments that mentions it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-19drivers:net:fsl-mc: Update MC address calculationPrabhakar Kushwaha
Update MC address caluclation as per MC design requirement of address as least significant 512MB address of MC private allocated memory. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
2017-07-19fsl/usb: enable errata-a010151 for ls2088a and ls2081aSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
2017-07-19usb: ums: support multiple controllers using controller_indexRajesh Bhagat
Adds a new field in fsg_common namely controller_index to support multiple controllers usb gadget support. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
2017-07-19usb: dwc3: Add helper functions to enable snooping and burst settingsRajat Srivastava
Adds helper functions to enable snooping and outstanding burst beat settings. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2017-07-18spi: fsl_qspi: Add 4bytes address supportSuresh Gupta
The QSPI support the direct 4bytes address command for flash read/write/erase. And the address can cover the whole QSPI memory space. signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-07-18sf: add ADDR_4B for 4byte address supportSuresh Gupta
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address. Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-07-18sf: Fix s25fs512s erase size and remove SECT_4K flagSuresh Gupta
As per data sheet, S25FS512S support Uniform sector option or erase size of 256 kbytes and Page Programming buffer of 256 or 512 Bytes. So, flag SECT_4K have no significance for this flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
2017-07-08powerpc, 8xx: Add support for MCR3000 board from CSSIChristophe Leroy
CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000 and CMPC885 which are respectively based on MPC866 and MPC885 processors. This patch adds support for the first board. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-08powerpc, 8xx: move Serial driver to drivers/serial/Christophe Leroy
At the same time, move to Kconfig Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
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