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Adding fdtdec_get_uint function which is the
unsigned version for fdtdec_get_int
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Heiko Schocher <hs@denx.de>
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This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox <adrian at humboldt dot co dot uk>
Signed-off-by: Andy Fleming <afleming@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Update this driver to use driver model and change all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Production boards should not use CONFIG_OF_EMBED. Fix this for the Zybo
boards.
The image to use now becomes u-boot-dtb.bin.
For example, the .bif file should contain a line like:
[load = 0x04000000,startup=0x04000000]/path/to/u-boot-dtb.bin
instead of:
[load = 0x04000000,startup=0x04000000]/path/to/u-boot.bin
When device tree is enabled we need to load u-boot-dtb.img. Change the
settings so that SPL does the right thing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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At present in SPL we place the device tree immediately after BSS. This
avoids needing to copy it out of the way before BSS can be used. However on
some boards BSS is not placed with the image - e.g. it can be in RAM if
available.
Add an option to tell U-Boot that the device tree should be placed at the
end of the image binary (_image_binary_end) instead of at the end of BSS.
Note: A common reason to place BSS in RAM is to support the FAT filesystem.
We should update the code so that it does not use so much BSS.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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It is sometimes useful to find a property in the chosen node. Add a function
for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Enable CONFIG_SYS_I2C_ZYNQ only if it has either I2C0 or I2C1
enabled in a board config.This fixes the issue of i2c error
during board init if board specific doesnt have either I2C0
or I2C1.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This adds support to update firmware on qspi flash using DFU.
On device:
=> setenv dfu_alt_info ${dfu_alt_info_qspi}
=> dfu 0 sf 0:0
On host:
$ sudo dfu-util -l
$ sudo dfu-util -D MLO -a MLO
$ sudo dfu-util -D u-boot.img -a u-boot.img
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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On T1040D4RDB board, u-boot fails to connect port FM1@DTSEC3 to
the Ethernet PHY because the wrong PHY address is used. Also,
T1040D4RDB supports SGMII on one port only.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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As sama5 board has 32k sram size, so the at91bootstrap and spl for sama5
boards is bigger than 16k (0x4000). That will overlap the U-Boot
environment. So I move environment to 0x6000. And reduce its size as
well.
Following shows the size of the spl binaries (v2015.04 vs v2015.07):
% ls v2015.04/*spi*spl.bin -l | awk '{print $5,$(NF)}'
15540 v2015.04/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin
15704 v2015.04/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin
16064 v2015.04/sama5d3xek_spiflash_defconfig_u-boot-spl.bin
16304 v2015.04/sama5d4ek_spiflash_defconfig_u-boot-spl.bin
16304 v2015.04/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin
% ls v2015.07/*spi*spl.bin -l | awk '{print $5,$(NF)}'
16136 v2015.07/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin
16300 v2015.07/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin
16664 v2015.07/sama5d3xek_spiflash_defconfig_u-boot-spl.bin
16904 v2015.07/sama5d4ek_spiflash_defconfig_u-boot-spl.bin
16904 v2015.07/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin
The gcc version is: gcc 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1)
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Bo Shen <voice.shen@gmail.com>
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As more features are added for SD boot on LS1021A QDS board,
the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
needs to be adjusted to a suitable value.
Starting address of the malloc pool used in SPL needs to be
adjusted too, or it will occupy the address u-boot loads.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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I2C1 can work on ls102xa rev2.0 SD boot, so add
ID EEPROM for SD boot.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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SR_IE(Self-refresh interrupt enable) is needed for
Hardware Based Self-Refresh. Make it configurable and let
board code handle the rest.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
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Currently there is no API to uninitialize mdio. Add two APIs for this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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The net_boot_file_name buffer is used as storage for the bootfilename
command line argument to network boot commands such as tftp and nfs.
Increase the size of this buffer to 1024 bytes as the current size of
128 bytes is restrictive for arbitrary paths on the server.
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
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Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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For most PPC platforms, they will call the first get_clocks() in
init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is
then defined to call the second get_clocks(), which should be
redundant for PPC.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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To support on board Aquantia's PHY AQR405.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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As we don't modify the 'name' parameter, so change it to const.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: John Otken <jotken@softadvances.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch changes the cword union to use specific length types that are
architecture indepented.
This patch also renames the members of the cword union to represent
their usage, i.e.:
c -> w8
s -> w16
l -> w32
ll -> w64
Where "w" stands for "width" in bits.
I discovered this problem when enabling CFI flash on vexpress64.
cword.l was an unsigned long int, but it was intended to be 32 bits wide.
Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a
64-bit system fails when attempting to use 32-bit wide CFI flash parts.
Similar problems also existed with the other cword sizes.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stefan Roese <sr@denx.de>
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As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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