summaryrefslogtreecommitdiff
path: root/arch/arm/dts/imx6dl.dtsi
blob: 9a4c22c2dade10e27aa19f3527c54b41f71f2e13 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"

/ {
	aliases {
		i2c3 = &i2c4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				996000  1250000
				792000  1175000
				396000  1150000
			>;
			fsl,soc-operating-points = <
				/* ARM kHz  SOC-PU uV */
				996000	1175000
				792000	1175000
				396000	1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks IMX6QDL_CLK_ARM>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
				 <&clks IMX6QDL_CLK_STEP>,
				 <&clks IMX6QDL_CLK_PLL1_SW>,
				 <&clks IMX6QDL_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			pu-supply = <&reg_pu>;
			soc-supply = <&reg_soc>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		ocram: sram@00900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x20000>;
			clocks = <&clks IMX6QDL_CLK_OCRAM>;
		};

		aips1: aips-bus@02000000 {
			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6dl-iomuxc";
			};

			pxp: pxp@020f0000 {
				reg = <0x020f0000 0x4000>;
				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
			};

			epdc: epdc@020f4000 {
				reg = <0x020f4000 0x4000>;
				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			};

			lcdif: lcdif@020f8000 {
				reg = <0x020f8000 0x4000>;
				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		aips2: aips-bus@02100000 {
			i2c4: i2c@021f8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
				reg = <0x021f8000 0x4000>;
				interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6DL_CLK_I2C4>;
				status = "disabled";
			};
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&ipu1_di0>, <&ipu1_di1>;
	};

	gpu-subsystem {
		compatible = "fsl,imx-gpu-subsystem";
		cores = <&gpu_2d>, <&gpu_3d>;
	};
};

&gpt {
	compatible = "fsl,imx6dl-gpt";
};

&hdmi {
	compatible = "fsl,imx6dl-hdmi";
};

&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel",
		      "di0", "di1";
};

&vpu {
	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};