summaryrefslogtreecommitdiff
path: root/arch/arm/dts/stv0991.dts
blob: 556df821e4e36f2167f50d9d021f0f18d7a551b5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
/dts-v1/;

/ {
	model = "ST STV0991 application board";
	compatible = "st,stv0991";
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
		stdout-path = &uart0;
	};

	memory {
		device_type="memory";
		reg = <0x0 0x198000>;
	};

	uart0: serial@0x80406000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x80406000 0x1000>;
		clock = <2700000>;
	};

	aliases {
		spi0 = "/spi@80203000";		/* QSPI */
	};

	qspi: spi@80203000 {
			compatible = "cadence,qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80203000 0x100>,
				<0x40000000 0x1000000>;
			clocks = <3750000>;
			ext-decoder = <0>; /* external decoder */
			num-cs = <4>;
			fifo-depth = <256>;
			sram-size = <256>;
			bus-num = <0>;
			status = "okay";

			flash0: n25q32@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spi-flash";
				reg = <0>;		/* chip select */
				spi-max-frequency = <50000000>;
				m25p,fast-read;
				page-size = <256>;
				block-size = <16>; 	/* 2^16, 64KB */
				read-delay = <4>;	/* delay value in read data capture register */
				tshsl-ns = <50>;
				tsd2d-ns = <50>;
				tchsh-ns = <4>;
				tslch-ns = <4>;
			};
	};
};