blob: 30f0bbeb890943347d07d4b635408c05ee871bea (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
/*
* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYSTEM_MANAGER_H_
#define _SYSTEM_MANAGER_H_
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
#define SYSMGR_ECC_OCRAM_EN (1 << 0)
#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
#define SYSMGR_FPGAINTF_USEFPGA 0x1
#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
#define SYSMGR_FPGAINTF_NAND (1 << 4)
#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
/* EMAC Group Bit definitions */
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/system_manager_gen5.h>
#endif
#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
#endif /* _SYSTEM_MANAGER_H_ */
|
