summaryrefslogtreecommitdiff
path: root/cpu/mpc83xx/cpu.c
blob: e934ba638fef62e99ff6ce635c8f9cef4611f59e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
/*
 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code for the MPC83xx family.
 *
 * Derived from the MPC8260 and MPC85xx.
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc83xx.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#endif

DECLARE_GLOBAL_DATA_PTR;


int checkcpu(void)
{
	volatile immap_t *immr;
	ulong clock = gd->cpu_clk;
	u32 pvr = get_pvr();
	u32 spridr;
	char buf[32];

	immr = (immap_t *)CFG_IMMR;

	if ((pvr & 0xFFFF0000) != PVR_83xx) {
		puts("Not MPC83xx Family!!!\n");
		return -1;
	}

	spridr = immr->sysconf.spridr;
	puts("CPU: ");
	switch(spridr) {
	case SPR_8349E_REV10:
	case SPR_8349E_REV11:
	case SPR_8349E_REV31:
		puts("MPC8349E, ");
		break;
	case SPR_8349_REV10:
	case SPR_8349_REV11:
	case SPR_8349_REV31:
		puts("MPC8349, ");
		break;
	case SPR_8347E_REV10_TBGA:
	case SPR_8347E_REV11_TBGA:
	case SPR_8347E_REV31_TBGA:
	case SPR_8347E_REV10_PBGA:
	case SPR_8347E_REV11_PBGA:
	case SPR_8347E_REV31_PBGA:
		puts("MPC8347E, ");
		break;
	case SPR_8347_REV10_TBGA:
	case SPR_8347_REV11_TBGA:
	case SPR_8347_REV31_TBGA:
	case SPR_8347_REV10_PBGA:
	case SPR_8347_REV11_PBGA:
	case SPR_8347_REV31_PBGA:
		puts("MPC8347, ");
		break;
	case SPR_8343E_REV10:
	case SPR_8343E_REV11:
	case SPR_8343E_REV31:
		puts("MPC8343E, ");
		break;
	case SPR_8343_REV10:
	case SPR_8343_REV11:
	case SPR_8343_REV31:
		puts("MPC8343, ");
		break;
	case SPR_8360E_REV10:
	case SPR_8360E_REV11:
	case SPR_8360E_REV12:
	case SPR_8360E_REV20:
		puts("MPC8360E, ");
		break;
	case SPR_8360_REV10:
	case SPR_8360_REV11:
	case SPR_8360_REV12:
	case SPR_8360_REV20:
		puts("MPC8360, ");
		break;
	case SPR_8323E_REV10:
	case SPR_8323E_REV11:
		puts("MPC8323E, ");
		break;
	case SPR_8323_REV10:
	case SPR_8323_REV11:
		puts("MPC8323, ");
		break;
	case SPR_8321E_REV10:
	case SPR_8321E_REV11:
		puts("MPC8321E, ");
		break;
	case SPR_8321_REV10:
	case SPR_8321_REV11:
		puts("MPC8321, ");
		break;
	default:
		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
		return 0;
	}

#if defined(CONFIG_MPC834X)
	/* Multiple revisons of 834x processors may have the same SPRIDR value.
	 * So use PVR to identify the revision number.
	 */
	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
#else
	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
#endif
	return 0;
}


/*
 * Program a UPM with the code supplied in the table.
 *
 * The 'dummy' variable is used to increment the MAD. 'dummy' is
 * supposed to be a pointer to the memory of the device being
 * programmed by the UPM.  The data in the MDR is written into
 * memory and the MAD is incremented every time there's a read
 * from 'dummy'. Unfortunately, the current prototype for this
 * function doesn't allow for passing the address of this
 * device, and changing the prototype will break a number lots
 * of other code, so we need to use a round-about way of finding
 * the value for 'dummy'.
 *
 * The value can be extracted from the base address bits of the
 * Base Register (BR) associated with the specific UPM.  To find
 * that BR, we need to scan all 8 BRs until we find the one that
 * has its MSEL bits matching the UPM we want.  Once we know the
 * right BR, we can extract the base address bits from it.
 *
 * The MxMR and the BR and OR of the chosen bank should all be
 * configured before calling this function.
 *
 * Parameters:
 * upm: 0=UPMA, 1=UPMB, 2=UPMC
 * table: Pointer to an array of values to program
 * size: Number of elements in the array.  Must be 64 or less.
 */
void upmconfig (uint upm, uint *table, uint size)
{
#if defined(CONFIG_MPC834X)
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile lbus83xx_t *lbus = &immap->lbus;
	volatile uchar *dummy = NULL;
	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */
	uint i;

	/* Scan all the banks to determine the base address of the device */
	for (i = 0; i < 8; i++) {
		if ((lbus->bank[i].br & BR_MSEL) == msel) {
			dummy = (uchar *) (lbus->bank[i].br & BR_BA);
			break;
		}
	}

	if (!dummy) {
		printf("Error: %s() could not find matching BR\n", __FUNCTION__);
		hang();
	}

	/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;

	for (i = 0; i < size; i++) {
		lbus->mdr = table[i];
		__asm__ __volatile__ ("sync");
		*dummy;	/* Write the value to memory and increment MAD */
		__asm__ __volatile__ ("sync");
	}

	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
	*mxmr &= 0xCFFFFFC0;
#else
	printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
	hang();
#endif
}


int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	ulong msr;
#ifndef MPC83xx_RESET
	ulong addr;
#endif

	volatile immap_t *immap = (immap_t *) CFG_IMMR;

#ifdef MPC83xx_RESET
	/* Interrupts and MMU off */
	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);

	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));

	/* enable Reset Control Reg */
	immap->reset.rpr = 0x52535445;
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* confirm Reset Control Reg is enabled */
	while(!((immap->reset.rcer) & RCER_CRE));

	printf("Resetting the board.");
	printf("\n");

	udelay(200);

	/* perform reset, only one bit */
	immap->reset.rcr = RCR_SWHR;

#else	/* ! MPC83xx_RESET */

	immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */

	/* Interrupts and MMU off */
	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);

	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));

	/*
	 * Trying to execute the next instruction at a non-existing address
	 * should cause a machine check, resulting in reset
	 */
	addr = CFG_RESET_ADDRESS;

	printf("resetting the board.");
	printf("\n");
	((void (*)(void)) addr) ();
#endif	/* MPC83xx_RESET */

	return 1;
}


/*
 * Get timebase clock frequency (like cpu_clk in Hz)
 */

unsigned long get_tbclk(void)
{
	ulong tbclk;

	tbclk = (gd->bus_clk + 3L) / 4L;

	return tbclk;
}


#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
	int re_enable = disable_interrupts();

	/* Reset the 83xx watchdog */
	volatile immap_t *immr = (immap_t *) CFG_IMMR;
	immr->wdt.swsrr = 0x556c;
	immr->wdt.swsrr = 0xaa39;

	if (re_enable)
		enable_interrupts ();
}
#endif

#if defined(CONFIG_OF_LIBFDT)

/*
 * "Setter" functions used to add/modify FDT entries.
 */
static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd)
{
	/*
	 * Fix it up if it exists, don't create it if it doesn't exist.
	 */
	if (fdt_get_property(fdt, nodeoffset, name, 0)) {
		return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6);
	}
	return -FDT_ERR_NOTFOUND;
}
#ifdef CONFIG_HAS_ETH1
/* second onboard ethernet port */
static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd)
{
	/*
	 * Fix it up if it exists, don't create it if it doesn't exist.
	 */
	if (fdt_get_property(fdt, nodeoffset, name, 0)) {
		return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6);
	}
	return -FDT_ERR_NOTFOUND;
}
#endif
#ifdef CONFIG_HAS_ETH2
/* third onboard ethernet port */
static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd)
{
	/*
	 * Fix it up if it exists, don't create it if it doesn't exist.
	 */
	if (fdt_get_property(fdt, nodeoffset, name, 0)) {
		return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6);
	}
	return -FDT_ERR_NOTFOUND;
}
#endif
#ifdef CONFIG_HAS_ETH3
/* fourth onboard ethernet port */
static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd)
{
	/*
	 * Fix it up if it exists, don't create it if it doesn't exist.
	 */
	if (fdt_get_property(fdt, nodeoffset, name, 0)) {
		return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6);
	}
	return -FDT_ERR_NOTFOUND;
}
#endif

static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd)
{
	u32  tmp;
	/*
	 * Create or update the property.
	 */
	tmp = cpu_to_be32(bd->bi_busfreq);
	return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}

/*
 * Fixups to the fdt.  If "create" is TRUE, the node is created
 * unconditionally.  If "create" is FALSE, the node is updated
 * only if it already exists.
 */
static const struct {
	char *node;
	char *prop;
	int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd);
} fixup_props[] = {
	{	"/cpus/" OF_CPU,
		 "bus-frequency",
		fdt_set_busfreq
	},
	{	"/cpus/" OF_SOC,
		"bus-frequency",
		fdt_set_busfreq
	},
	{	"/" OF_SOC "/serial@4500/",
		"clock-frequency",
		fdt_set_busfreq
	},
	{	"/" OF_SOC "/serial@4600/",
		"clock-frequency",
		fdt_set_busfreq
	},
#ifdef CONFIG_MPC83XX_TSEC1
	{	"/" OF_SOC "/ethernet@24000,
		"mac-address",
		fdt_set_eth0
	},
	{	"/" OF_SOC "/ethernet@24000,
		"local-mac-address",
		fdt_set_eth0
	},
#endif
#ifdef CONFIG_MPC83XX_TSEC2
	{	"/" OF_SOC "/ethernet@25000,
		"mac-address",
		fdt_set_eth1
	},
	{	"/" OF_SOC "/ethernet@25000,
		"local-mac-address",
		fdt_set_eth1
	},
#endif
#ifdef CONFIG_UEC_ETH1
#if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
	{	"/" OF_QE "/ucc@2000/mac-address",
		"mac-address",
		fdt_set_eth0
	},
	{	"/" OF_QE "/ucc@2000/mac-address",
		"local-mac-address",
		fdt_set_eth0
	},
#elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
	{	"/" OF_QE "/ucc@2200/mac-address",
		"mac-address",
		fdt_set_eth0
	},
	{	"/" OF_QE "/ucc@2200/mac-address",
		"local-mac-address",
		fdt_set_eth0
	},
#endif
#endif
#ifdef CONFIG_UEC_ETH2
#if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
	{	"/" OF_QE "/ucc@3000/mac-address",
		"mac-address",
		fdt_set_eth1
	},
	{	"/" OF_QE "/ucc@3000/mac-address",
		"local-mac-address",
		fdt_set_eth1
	},
#elif CFG_UEC1_UCC_NUM == 3  /* UCC4 */
	{	"/" OF_QE "/ucc@3200/mac-address",
		"mac-address",
		fdt_set_eth1
	},
	{	"/" OF_QE "/ucc@3200/mac-address",
		"local-mac-address",
		fdt_set_eth1
	},
#endif
#endif
};

void
ft_cpu_setup(void *blob, bd_t *bd)
{
	int  nodeoffset;
	int  err;
	int  j;

	for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
		nodeoffset = fdt_path_offset(fdt, fixup_props[j].node);
		if (nodeoffset >= 0) {
			err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd);
			if (err < 0)
				printf("set_fn/libfdt: %s %s returned %s\n",
					fixup_props[j].node,
					fixup_props[j].prop,
					fdt_strerror(err));
		}
	}
}
#endif

#if defined(CONFIG_OF_FLAT_TREE)
void
ft_cpu_setup(void *blob, bd_t *bd)
{
	u32 *p;
	int len;
	ulong clock;

	clock = bd->bi_busfreq;
	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

	p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

	p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

#ifdef CONFIG_MPC83XX_TSEC1
	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enetaddr, 6);

	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enetaddr, 6);
#endif

#ifdef CONFIG_MPC83XX_TSEC2
	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enet1addr, 6);

	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enet1addr, 6);
#endif

#ifdef CONFIG_UEC_ETH1
#if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enetaddr, 6);

	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enetaddr, 6);
#elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enetaddr, 6);

	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enetaddr, 6);
#endif
#endif

#ifdef CONFIG_UEC_ETH2
#if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enet1addr, 6);

	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enet1addr, 6);
#elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enet1addr, 6);

	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
	if (p != NULL)
		memcpy(p, bd->bi_enet1addr, 6);
#endif
#endif
}
#endif

#if defined(CONFIG_DDR_ECC)
void dma_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile dma83xx_t *dma = &immap->dma;
	volatile u32 status = swab32(dma->dmasr0);
	volatile u32 dmamr0 = swab32(dma->dmamr0);

	debug("DMA-init\n");

	/* initialize DMASARn, DMADAR and DMAABCRn */
	dma->dmadar0 = (u32)0;
	dma->dmasar0 = (u32)0;
	dma->dmabcr0 = 0;

	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* clear CS bit */
	dmamr0 &= ~DMA_CHANNEL_START;
	dma->dmamr0 = swab32(dmamr0);
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* while the channel is busy, spin */
	while(status & DMA_CHANNEL_BUSY) {
		status = swab32(dma->dmasr0);
	}

	debug("DMA-init end\n");
}

uint dma_check(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile dma83xx_t *dma = &immap->dma;
	volatile u32 status = swab32(dma->dmasr0);
	volatile u32 byte_count = swab32(dma->dmabcr0);

	/* while the channel is busy, spin */
	while (status & DMA_CHANNEL_BUSY) {
		status = swab32(dma->dmasr0);
	}

	if (status & DMA_CHANNEL_TRANSFER_ERROR) {
		printf ("DMA Error: status = %x @ %d\n", status, byte_count);
	}

	return status;
}

int dma_xfer(void *dest, u32 count, void *src)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile dma83xx_t *dma = &immap->dma;
	volatile u32 dmamr0;

	/* initialize DMASARn, DMADAR and DMAABCRn */
	dma->dmadar0 = swab32((u32)dest);
	dma->dmasar0 = swab32((u32)src);
	dma->dmabcr0 = swab32(count);

	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* init direct transfer, clear CS bit */
	dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
			DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
			DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);

	dma->dmamr0 = swab32(dmamr0);

	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* set CS to start DMA transfer */
	dmamr0 |= DMA_CHANNEL_START;
	dma->dmamr0 = swab32(dmamr0);
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	return ((int)dma_check());
}
#endif /*CONFIG_DDR_ECC*/