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| author | Stephen Warren <swarren@nvidia.com> | 2016-08-05 22:10:34 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-08-15 17:26:13 (GMT) |
| commit | bbc5b36b2519d5aaa267a2bffba4b3e44dc8f51c (patch) | |
| tree | 3c1e7d785a68053e1acd917542927b05e4a85b9a /.travis.yml | |
| parent | c04930762d433aeef94d8c910fa65461d43b9016 (diff) | |
| download | u-boot-fsl-qoriq-bbc5b36b2519d5aaa267a2bffba4b3e44dc8f51c.tar.xz | |
pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.
On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions