85xx: Added PCIe support for P1 P2 RDB

Call fsl_pci_init_port() to initialize all the PCIe ports on the board.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

3 files changed, 125 insertions, 1 deletions

diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
index 9107263..ad1b769 100644
--- a/board/freescale/p1_p2_rdb/Makefile
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
 COBJS-y	+= law.o
+COBJS-$(CONFIG_PCI)  += pci.o
 COBJS-y	+= tlb.o
-COBJS-y	+= ddr.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
new file mode 100644
index 0000000..174a8a7
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+void pci_init_board(void)
+{
+	struct fsl_pci_info pci_info[2];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint devdisr = in_be32(&gur->devdisr);
+	uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+	int num = 0;
+	int first_free_busno = 0;
+
+	int pcie_ep, pcie_configured;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+			devdisr, io_sel, host_agent);
+
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+		printf ("    eTSEC2 is in sgmii mode.\n");
+
+#ifdef CONFIG_PCIE2
+	SET_STD_PCIE_INFO(pci_info[num], 2);
+	pcie_ep = (host_agent == 2) || (host_agent == 4) ||
+		(host_agent == 6) || (host_agent == 0);
+	pcie_configured  = (io_sel == 0xE);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		puts ("\n    PCIE2 connected to Slot 1 as ");
+		printf ("%s (base address %lx)",
+			pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num],
+					&pcie2_hose, first_free_busno);
+		num++;
+	} else {
+		printf ("    PCIE2: disabled\n");
+	}
+#else
+	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+	SET_STD_PCIE_INFO(pci_info[num], 1);
+
+	pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
+		(host_agent == 5);
+	pcie_configured  = (io_sel == 0xE);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		puts ("\n    PCIE1 connected to Slot 2 as ");
+		printf ("%s (base address %lx)",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num],
+					&pcie1_hose, first_free_busno);
+		num++;
+	} else {
+		printf ("    PCIE1: disabled\n");
+	}
+#else
+	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+}
+
+void ft_pci_board_setup(void *blob)
+{
+/* According to h/w manual, PCIE2 is at lower address(0x9000)
+ * than PCIE1(0xa000).
+ * Hence PCIE2 is made to occupy the pci1 position in dts to
+ * keep the addresses sorted there.
+ * Generally the case with all FSL SOCs.
+ */
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+}
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 9591641..6d44d6c 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -35,6 +35,12 @@
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
 #define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE