diff options
author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2013-09-24 06:38:33 (GMT) |
---|---|---|
committer | Joe Hershberger <joe.hershberger@ni.com> | 2013-11-22 22:50:54 (GMT) |
commit | 47ce8890486be72ce6b634c590a0c6baa2447084 (patch) | |
tree | afc533e655fa9b7e522ce17f56686d77aabb5c5c | |
parent | dfcaa61c33e1fc5f737318cfdbcf7f7b49f237a3 (diff) | |
download | u-boot-fsl-qoriq-47ce8890486be72ce6b634c590a0c6baa2447084.tar.xz |
net: sh-eth: Add support R8A7791
R8A7791 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7791.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Joe Hershberger <joe.hershberger@gmail.com>
-rw-r--r-- | drivers/net/sh_eth.c | 5 | ||||
-rw-r--r-- | drivers/net/sh_eth.h | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 9020752..5e132f2 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -410,7 +410,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); #endif /* Configure phy */ @@ -435,7 +435,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(eth, 1, RTRATE); -#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) +#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ + defined(CONFIG_R8A7791) val = ECMR_RTM; #endif } else if (phy->speed == 10) { diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 43b8ac9..8aa7109 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -301,7 +301,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7740) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xE9A00000 -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xEE700200 #endif @@ -507,7 +507,7 @@ enum FELIC_MODE_BIT { ECMR_PRM = 0x00000001, #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) ECMR_RTM = 0x00000004, #endif |