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author | Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com> | 2014-01-08 20:18:14 (GMT) |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-01-10 14:18:33 (GMT) |
commit | 86737bcf07e595e78620d29b429ad9e994a32659 (patch) | |
tree | a71636f86699f1198ba1c4610044c9d5ac59c4c4 | |
parent | 796d49969e2674f1f2ab8564ccc7b6cb62892e38 (diff) | |
download | u-boot-fsl-qoriq-86737bcf07e595e78620d29b429ad9e994a32659.tar.xz |
zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs
CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-rw-r--r-- | include/configs/zynq-common.h | 1 | ||||
-rw-r--r-- | include/configs/zynq_zc70x.h | 2 | ||||
-rw-r--r-- | include/configs/zynq_zed.h | 2 |
3 files changed, 4 insertions, 1 deletions
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bce1094..bb9e337 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -125,7 +125,6 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 9910804..6950d41 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_ZYNQ_ZC70X_H #define __CONFIG_ZYNQ_ZC70X_H +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + #define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 278db1e..31926df 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_ZYNQ_ZED_H #define __CONFIG_ZYNQ_ZED_H +#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) + #define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 |