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| author | Niklaus Giger <niklaus.giger@netstal.com> | 2008-02-05 09:26:41 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-02-16 05:39:46 (GMT) |
| commit | 8cc10d06b833ed917a19ad358c8ebbed8bc19555 (patch) | |
| tree | c6bd63772a3ad0615c80952651ba40689bca753a | |
| parent | 214398d9cb22268d9d4f7563359edca0f78297a2 (diff) | |
| download | u-boot-fsl-qoriq-8cc10d06b833ed917a19ad358c8ebbed8bc19555.tar.xz | |
ppc4xx: PPC405GPr fix missing register definitions
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
| -rw-r--r-- | include/ppc405.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index b5ad38f..cbfe89e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -784,6 +784,14 @@ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ + +/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ +#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#define CPC0_ECR (0xaa) /* edge conditioner register */ + #define ecr (0xaa) /* edge conditioner register (405gpr) */ /* Bit definitions */ |