diff options
author | wdenk <wdenk> | 2004-06-10 21:34:36 (GMT) |
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committer | wdenk <wdenk> | 2004-06-10 21:34:36 (GMT) |
commit | b54d32b40d95d399dd1f53f24c93b0cf5c42460d (patch) | |
tree | dba569eef315497f378c460e0e72ce98df053dd1 | |
parent | 681334540d109558fe7c382faf9c705439c2dfa3 (diff) | |
download | u-boot-fsl-qoriq-b54d32b40d95d399dd1f53f24c93b0cf5c42460d.tar.xz |
* Patch by Robert Schwebel, 10 Jun 2004:
Add support for Intel K3 strata flash.
* Some cleanup
* Patch by Thomas Brand, 10 Jun 2004:
Fix "loads" command on DK1S10 board
-rw-r--r-- | CHANGELOG | 6 | ||||
-rw-r--r-- | board/ispan/ispan.c | 2 | ||||
-rw-r--r-- | board/mx1ads/syncflash.c | 32 | ||||
-rw-r--r-- | common/cmd_jffs2.c | 2 | ||||
-rw-r--r-- | include/bmp_logo.h | 2 | ||||
-rw-r--r-- | include/configs/DK1S10.h | 1 | ||||
-rw-r--r-- | include/configs/FADS823.h | 3 | ||||
-rw-r--r-- | include/configs/FADS850SAR.h | 3 | ||||
-rw-r--r-- | include/flash.h | 25 |
9 files changed, 43 insertions, 33 deletions
@@ -2,6 +2,12 @@ Changes since U-Boot 1.1.1: ====================================================================== +* Patch by Robert Schwebel, 10 Jun 2004: + Add support for Intel K3 strata flash. + +* Patch by Thomas Brand, 10 Jun 2004: + Fix "loads" command on DK1S10 board + * Patch by Yuli Barcohen, 09 Jun 2004: Add support for 8MB flash SIMM and JFFS2 file system on Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c index e41a7c4..fd34899 100644 --- a/board/ispan/ispan.c +++ b/board/ispan/ispan.c @@ -236,6 +236,7 @@ static int seeprom_read (int addr, uchar * data, int size) * Serial EEPROM conected to the PSpan bridge. We keep it as * simple as possible. */ +#ifdef DEBUG static int hwc_flash_size (void) { uchar byte; @@ -273,6 +274,7 @@ static int hwc_local_sdram_size (void) } return -1; } +#endif /* DEBUG */ static int hwc_main_sdram_size (void) { diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index afbe786..fc1d7f6 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -33,26 +33,26 @@ typedef unsigned long * p_u32; flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Following Setting is for CSD1 */ -#define SFCTL 0x00221004 -#define reg_SFCTL __REG(SFCTL) +#define SFCTL 0x00221004 +#define reg_SFCTL __REG(SFCTL) -#define SYNCFLASH_A10 (0x00100000) +#define SYNCFLASH_A10 (0x00100000) -#define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) +#define CMD_NORMAL (0x81020300) /* Normal Mode */ +#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ +#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ +#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ +#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ +#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) -#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ +#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ /* LCR Command */ -#define LCR_READSTATUS (0x0001C000) /* 0x70 */ -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ +#define LCR_READSTATUS (0x0001C000) /* 0x70 */ +#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ +#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ +#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ +#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ /* Get Status register */ @@ -330,5 +330,3 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { return ERR_OK; } - - diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 207c211..27e7273 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -103,7 +103,7 @@ jffs2_part_info(int part_num) memset(&part, 0, sizeof(part)); - part.offset = CONFIG_JFFS2_NAND_OFF; + part.offset = (char *)CONFIG_JFFS2_NAND_OFF; part.size = CONFIG_JFFS2_NAND_SIZE; /* the bigger size the slower jffs2 */ #ifndef CONFIG_JFFS2_NAND_DEV diff --git a/include/bmp_logo.h b/include/bmp_logo.h index 9c924b8..265f744 100644 --- a/include/bmp_logo.h +++ b/include/bmp_logo.h @@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = { 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, - 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, + 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, }; unsigned char bmp_logo_bitmap[] = { diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index b2e86c8..e79eb49 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -142,6 +142,7 @@ #if (CFG_NIOS_CPU_UART_NUMS != 0) #define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #if (CFG_NIOS_CPU_UART0_BR != 0) #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 4f3d397..726ab37 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -366,8 +366,9 @@ #define BCSR1_PCCVCC1 ((uint)0x00010000) #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) +#define BCSR2_DRAM_PD_SHIFT 23 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000) #define BCSR2_DBREVNR_MASK ((uint)0x00030000) diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index 9e292ae..2a986f0 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -333,8 +333,9 @@ #define BCSR1_PCCVCC1 ((uint)0x00010000) #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) +#define BCSR2_DRAM_PD_SHIFT 23 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000) #define BCSR2_DBREVNR_MASK ((uint)0x00030000) diff --git a/include/flash.h b/include/flash.h index ddba7e5..51a7ae0 100644 --- a/include/flash.h +++ b/include/flash.h @@ -248,9 +248,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */ #define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */ #define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */ -#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ -#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ -#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ @@ -330,10 +330,6 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ #define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ -#define FLASH_28F320J3A 0x007C /* INTEL 28F320J3A ( 32M = 128K x 32) */ -#define FLASH_28F640J3A 0x007D /* INTEL 28F640J3A ( 64M = 128K x 64) */ -#define FLASH_28F128J3A 0x007E /* INTEL 28F128J3A (128M = 128K x 128) */ - #define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ #define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ #define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ @@ -364,15 +360,20 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ #define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ #define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ -/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ -#define FLASH_28F256L18T 0x00B0 -#define FLASH_28F256K3 0x00A8 +#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ #define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ #define FLASH_AMDL163B 0x00B3 +#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */ +#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */ +#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */ + +#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ +#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ +#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ -#define FLASH_FUJLV650 0x00B4 /* Fujitsu MBM 29LV650UE/651UE */ +#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ +#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ -#define FLASH_MT28S4M16LC 0x00B5 /* Micron MT28S4M16LC */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ |