diff options
| author | York Sun <yorksun@freescale.com> | 2014-09-05 05:52:41 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 17:30:34 (GMT) |
| commit | d28cb6714216cc9e6bfdc1fa333d5dcd174207bd (patch) | |
| tree | ce6fe8fcaf3297e38b8330d8d5bdbb345c2f63f6 | |
| parent | 19060bd886381a58cfe335c2f13b6111ed936dd5 (diff) | |
| download | u-boot-fsl-qoriq-d28cb6714216cc9e6bfdc1fa333d5dcd174207bd.tar.xz | |
driver/ddr/freescale: Add support of accumulate ECC
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 04e4178..5e0ee77 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int x32_en = 0; /* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ unsigned int mem_halt = 0; /* memory controller halt */ unsigned int bi = 0; /* Bypass initialization */ @@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts->ba_intlv_ctl; hse = popts->half_strength_driver_enable; + /* set when ddr bus width < 64 */ + acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; + ddr->ddr_sdram_cfg = (0 | ((mem_en & 0x1) << 31) | ((sren & 0x1) << 30) @@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en & 0x1) << 5) | ((pchb8 & 0x1) << 4) | ((hse & 0x1) << 3) + | ((acc_ecc_en & 0x1) << 2) | ((mem_halt & 0x1) << 1) | ((bi & 0x1) << 0) ); |