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| author | Christian Riesch <christian.riesch@omicron.at> | 2012-02-02 00:44:40 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 09:11:33 (GMT) |
| commit | d735a99d3b15daa8edfc10e52fa8860c06fe803c (patch) | |
| tree | c5556f646ac5f7c995567127beafe7dd405d4cdb | |
| parent | b67d8816fd62f0a379caa16846381b5a4e4de398 (diff) | |
| download | u-boot-fsl-qoriq-d735a99d3b15daa8edfc10e52fa8860c06fe803c.tar.xz | |
arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
| -rw-r--r-- | arch/arm/cpu/arm926ejs/start.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 525c112..6f05f1a 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -369,7 +369,8 @@ flush_dcache: mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ /* - * disable MMU and D cache, and enable I cache + * disable MMU and D cache + * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ @@ -380,7 +381,9 @@ flush_dcache: bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ +#ifndef CONFIG_SYS_ICACHE_OFF orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#endif mcr p15, 0, r0, c1, c0, 0 /* |