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authorTom Rini <trini@konsulko.com>2017-08-08 02:00:34 (GMT)
committerTom Rini <trini@konsulko.com>2017-08-08 21:02:31 (GMT)
commit1989374b21089c63019fc9648408c8d609023ffe (patch)
tree429c7284e4500562c315061ced6cd5f1e6b0f605 /README
parent6e7adf7037c76f081b149685fa5e978e2ddf2a22 (diff)
downloadu-boot-fsl-qoriq-1989374b21089c63019fc9648408c8d609023ffe.tar.xz
configs: Finish migration of PHY_GIGE
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'README')
-rw-r--r--README5
1 files changed, 0 insertions, 5 deletions
diff --git a/README b/README
index 1edf3db..3735916 100644
--- a/README
+++ b/README
@@ -1627,11 +1627,6 @@ The following options need to be configured:
The clock frequency of the MII bus
- CONFIG_PHY_GIGE
-
- If this option is set, support for speed/duplex
- detection of gigabit PHY is included.
-
CONFIG_PHY_RESET_DELAY
Some PHY like Intel LXT971A need extra delay after