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| author | SRICHARAN R <r.sricharan@ti.com> | 2012-03-12 02:25:37 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 06:31:23 (GMT) |
| commit | f40107345cbcd6e0d1747eda45e76c4e2a6df0db (patch) | |
| tree | 19926012178f2c73c3fc5c60d391d8d40f1cfaff /arch/arm/cpu/armv7/omap4 | |
| parent | 6ad8d67de8f9ec9d4a8a90b0b3f78f13bec43c89 (diff) | |
| download | u-boot-fsl-qoriq-f40107345cbcd6e0d1747eda45e76c4e2a6df0db.tar.xz | |
OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/sdram_elpida.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index a5ec7d3..b538960 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -89,6 +89,10 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .emif_ddr_phy_ctlr_1_init = 0x049ffff5, .emif_ddr_phy_ctlr_1 = 0x049ff418 }; + +/* Dummy registers for OMAP44xx */ +const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; + const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, |