diff options
| author | Stefan Roese <sr@denx.de> | 2014-11-07 12:50:30 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2014-11-07 15:09:10 (GMT) |
| commit | a877bec3ecd7961211a59b2c130e055e0f771976 (patch) | |
| tree | b4a94f10ecdcb027435a470c2c6232d9825ac39e /arch/arm/cpu/armv7 | |
| parent | d2bb937db911b19ed38dd4e5a30b5bf4f2e5a951 (diff) | |
| download | u-boot-fsl-qoriq-a877bec3ecd7961211a59b2c130e055e0f771976.tar.xz | |
arm: socfpga: Add socfpga_spim_enable() to reset_manager.c
This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.
This function is called from arch_early_init_r() if the SPI
driver is enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/misc.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/reset_manager.c | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 8c3e5f7..73cffd3 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -202,6 +202,12 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + return 0; } diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 1d3a95d..af9db85 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable) #endif } } + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); +} |