diff options
| author | Dan Murphy <dmurphy@ti.com> | 2013-08-26 13:54:50 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2013-10-20 21:42:39 (GMT) |
| commit | d861a333da84dd7ab70e975171159c37f7d06939 (patch) | |
| tree | 32b1f7efee223c98f73aa78d6d6a9003af32545c /arch/arm/cpu/armv7 | |
| parent | 1bd435bc70a03f150900be4ac70a7bc8bfa4b438 (diff) | |
| download | u-boot-fsl-qoriq-d861a333da84dd7ab70e975171159c37f7d06939.tar.xz | |
ARM: OMAP5: Add registers and defines for USBOTG SS
Add the prcm registers and the bit definitions to enable the
USB SS port of the OMAP5 device.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ab0c568..bb77b5c 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -339,7 +339,7 @@ void configure_mpu_dpll(void) debug("MPU DPLL locked\n"); } -#ifdef CONFIG_USB_EHCI_OMAP +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) static void setup_usb_dpll(void) { const struct dpll_params *params; @@ -404,7 +404,7 @@ static void setup_dplls(void) /* MPU dpll */ configure_mpu_dpll(); -#ifdef CONFIG_USB_EHCI_OMAP +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) setup_usb_dpll(); #endif params = get_ddr_dpll_params(*dplls_data); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 764620d..e6686fd 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -295,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = { struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, + .control_phy_power_usb = 0x4A002370, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, @@ -567,6 +568,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640, .cm_coreaon_bandgap_clkctrl = 0x4a008648, .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, @@ -698,6 +700,8 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_p1500_clkctrl = 0x4a009678, .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0, /* prm irqstatus regs */ .prm_irqstatus_mpu_2 = 0x4ae06014, |