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| author | Mingkai Hu <Mingkai.Hu@freescale.com> | 2015-10-26 11:47:51 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-10-29 17:34:00 (GMT) |
| commit | 8281c58fd46d095e28e60b2fb0ce84b4444896f8 (patch) | |
| tree | f2e2bc68eb6d3fdcd7cc99a3718602206477029c /arch/arm/cpu/armv8/fsl-layerscape/Makefile | |
| parent | 9f3183d2d69f6d392fb943d249934f8648531e7e (diff) | |
| download | u-boot-fsl-qoriq-8281c58fd46d095e28e60b2fb0ce84b4444896f8.tar.xz | |
armv8/fsl_lsch2: Add fsl_lsch2 SoC
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/Makefile')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index ccb3aa5..4754e59 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -14,6 +14,11 @@ obj-$(CONFIG_SPL) += spl.o ifneq ($(CONFIG_FSL_LSCH3),) obj-y += fsl_lsch3_speed.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o +else +ifneq ($(CONFIG_FSL_LSCH2),) +obj-y += fsl_lsch2_speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o +endif endif ifneq ($(CONFIG_LS2085A),) |