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| author | Stephen Warren <swarren@nvidia.com> | 2016-10-19 21:18:46 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-11-07 22:36:29 (GMT) |
| commit | 1ab557a074aaa1927f7532489a1b75137e245b70 (patch) | |
| tree | 7419c580b01cfad546a1014b85aabf0f93f097c6 /arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | |
| parent | b9ae6415b6a099478c71fc3d410fc9a3776d7afa (diff) | |
| download | u-boot-fsl-qoriq-1ab557a074aaa1927f7532489a1b75137e245b70.tar.xz | |
armv8: add hooks for all cache-wide operations
SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..5700b1f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -245,7 +245,7 @@ hnf_set_pstate: ret -ENTRY(__asm_flush_l3_cache) +ENTRY(__asm_flush_l3_dcache) /* * Return status in x0 * success 0 @@ -275,7 +275,7 @@ ENTRY(__asm_flush_l3_cache) mov x0, x8 mov lr, x29 ret -ENDPROC(__asm_flush_l3_cache) +ENDPROC(__asm_flush_l3_dcache) #endif #ifdef CONFIG_MP |