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author | Prabhakar Kushwaha <prabhakar at freescale.com> | 2015-05-28 09:24:11 (GMT) |
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committer | York Sun <yorksun@freescale.com> | 2015-07-20 18:44:35 (GMT) |
commit | 092da485c7e685745b6e6f9ab5540fb002046201 (patch) | |
tree | 4653dfc8eb5d7a65db39c1b86eb8e969242c4884 /arch/arm/cpu/armv8 | |
parent | a2dc818f21cf216c486d267f7a983b8e7808519c (diff) | |
download | u-boot-fsl-qoriq-092da485c7e685745b6e6f9ab5540fb002046201.tar.xz |
armv8/ls2085a: Update SoC README for DDR layout
Update SoC README to provide details of
- Memory regions
- Memory used by MC and Debug server
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/README | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 37f07fb..3c15479 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -9,6 +9,31 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A. +DDR Layout +============ +Entire DDR region splits into two regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at 0x80_8000_0000 to the top of total memory, + for example 16GB, 0x83_ffff_ffff. + +All DDR memory is marked as cache-enabled. + +When MC and Debug server is enabled, they carve 512MB away from the high +end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB +with MC and Debug server enabled. Linux only sees 15.5GB. + +The reserved 512MB layout looks like + + +---------------+ <-- top/end of memory + | 256MB | debug server + +---------------+ + | 256MB | MC + +---------------+ + | ... | + +MC requires the memory to be aligned with 512MB, so even debug server is +not enabled, 512MB is reserved, not 256MB. + Flash Layout ============ |