diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-08-25 17:26:45 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-09-09 15:24:49 (GMT) |
| commit | 1b8ad74a6f8cea55a727dc4b399baac46d0daef1 (patch) | |
| tree | 0553356fd461dd173b74c9108577b60c997161af /arch/arm/cpu | |
| parent | ac17dcf653138cd0e521142fdfdfdff8027d3a04 (diff) | |
| download | u-boot-fsl-qoriq-1b8ad74a6f8cea55a727dc4b399baac46d0daef1.tar.xz | |
pcie_imx: Add mx6solox support
Let PCI on mx6solox also be supported.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index a861e65..52136f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -599,6 +599,7 @@ int enable_pcie_clock(void) struct anatop_regs *anatop_regs = (struct anatop_regs *)ANATOP_BASE_ADDR; struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 lvds1_clk_sel; /* * Here be dragons! @@ -608,17 +609,25 @@ int enable_pcie_clock(void) * marked as ANATOP_MISC1 is actually documented in the PMU section * of the datasheet as PMU_MISC1. * - * Switch LVDS clock source to SATA (0xb), disable clock INPUT and - * enable clock OUTPUT. This is important for PCI express link that - * is clocked from the i.MX6. + * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on + * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important + * for PCI express link that is clocked from the i.MX6. */ #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb + + if (is_cpu_type(MXC_CPU_MX6SX)) + lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; + else + lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; + clrsetbits_le32(&anatop_regs->ana_misc1, ANADIG_ANA_MISC1_LVDSCLK1_IBEN | ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, - ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel); /* PCIe reference clock sourced from AXI. */ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); |