diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2017-01-10 08:44:16 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-01-18 17:28:09 (GMT) |
| commit | 3564208e013d34eb0dab58d2f1561feee3f5735d (patch) | |
| tree | 4b228311b8d014148c450c36661681a7b812397b /arch/arm/cpu | |
| parent | 904110c7ac801b99029b2bca4765c792c9eac582 (diff) | |
| download | u-boot-fsl-qoriq-3564208e013d34eb0dab58d2f1561feee3f5735d.tar.xz | |
armv8/fsl-lsch3: consolidate the clock system initialization
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a9b12a4..f8fefc7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) #endif #endif + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; - /* Platform clock is half of platform PLL */ - sys_info->freq_systembus /= 2; sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; @@ -142,13 +141,13 @@ int get_clocks(void) struct sys_info sys_info; get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif #if defined(CONFIG_FSL_ESDHC) - gd->arch.sdhc_clk = gd->bus_clk / 2; + gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) @@ -159,7 +158,7 @@ int get_clocks(void) /******************************************** * get_bus_freq - * return system bus freq in Hz + * return platform clock in Hz *********************************************/ ulong get_bus_freq(ulong dummy) { @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) return gd->mem_clk; } +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; +} + +int get_serial_clock(void) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0) / 2; + return get_i2c_freq(0); case MXC_DSPI_CLK: - return get_bus_freq(0) / 2; + return get_dspi_freq(0); default: printf("Unsupported clock\n"); } |