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author | Tom Rini <trini@konsulko.com> | 2016-03-15 12:01:17 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2016-03-15 12:01:17 (GMT) |
commit | 4d339a9e8a758889de5da16b562aff5601bb3d8d (patch) | |
tree | 1c1ac403b33a156efbd8f42c8970d771a6ce8f5c /arch/arm/cpu | |
parent | e6de55ec5bf306df3b3cc8e7a4cc17fa1e78ca6c (diff) | |
parent | 00b1d2d3178747c113dd8f939cf3e2d449bfaf54 (diff) | |
download | u-boot-fsl-qoriq-4d339a9e8a758889de5da16b562aff5601bb3d8d.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-video
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a34675c..91a3deb 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -548,7 +548,8 @@ void imx_setup_hdmi(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - int reg; + int reg, count; + u8 val; /* Turn on HDMI PHY clock */ reg = readl(&mxc_ccm->CCGR2); @@ -565,6 +566,16 @@ void imx_setup_hdmi(void) |(CHSCCDR_IPU_PRE_CLK_540M_PFD << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); + + /* Clear the overflow condition */ + if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { + /* TMDS software reset */ + writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); + val = readb(&hdmi->fc_invidconf); + /* Need minimum 3 times to write to clear the register */ + for (count = 0 ; count < 5 ; count++) + writeb(val, &hdmi->fc_invidconf); + } } #endif |