diff options
| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2015-11-20 05:07:48 (GMT) |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-11-22 10:31:00 (GMT) |
| commit | 52d093112a307b2dd1ae46f8bd6ba7904760ac57 (patch) | |
| tree | a590cdeec5e083aa81f33686d30b10ac41a67afa /arch/arm/cpu | |
| parent | 0404d53f2f2024312b108a1b692bf668545b772b (diff) | |
| download | u-boot-fsl-qoriq-52d093112a307b2dd1ae46f8bd6ba7904760ac57.tar.xz | |
sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3
The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
This can be verified by reading the value of the AHB1_APB1_CFG_REG
register via /dev/mem. It always reads as 0x3180 regardless of
the current cpufreq operating point. So this configuration should
be safe for use in U-Boot too.
PLL6 also needs to be configured before it is used as the clock
source, according to the "CCU / Programming Guidelines" section
of the Allwinner manual.
The current low AHB1 clock speed is limiting the USB transfer
speed when booting via FEL. This patch can increase the FEL USB
transfer speed from ~510 KB/s to ~950 KB/s.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 3ab3b31..916ee48 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -34,9 +34,11 @@ void clock_init_safe(void) clock_set_pll1(408000000); - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) + ; + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); |