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authorStephen Warren <swarren@nvidia.com>2014-04-22 20:37:54 (GMT)
committerTom Warren <twarren@nvidia.com>2014-05-13 17:41:31 (GMT)
commitbb14469ae088682859411e45573d01ed11373960 (patch)
treefe8e32d6d1980309df19f0450fd099a59a4973aa /arch/arm/cpu
parenteceb3f26f407d65dae3902180b3c9f3128f0f349 (diff)
downloadu-boot-fsl-qoriq-bb14469ae088682859411e45573d01ed11373960.tar.xz
ARM: tegra: add function to enable input clamping on tristate
The HW-defined procedure for booting Tegra requires that CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux. Add a function to the pinmux driver to allow boards to do this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/tegra-common/pinmux-common.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
index 6d7a7d9..6e3ab0c 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -86,6 +86,22 @@
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
+#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+/* This register/field only exists on Tegra114 and later */
+#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
+#define CLAMP_INPUTS_WHEN_TRISTATED 1
+
+void pinmux_set_tristate_input_clamping(void)
+{
+ u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+ u32 val;
+
+ val = readl(reg);
+ val |= CLAMP_INPUTS_WHEN_TRISTATED;
+ writel(val, reg);
+}
+#endif
+
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
u32 *reg = MUX_REG(pin);