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| author | Saksham Jain <saksham.jain@nxp.com> | 2016-03-23 10:54:39 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-03-29 15:46:21 (GMT) |
| commit | 809d343a1a778e68d519c04e01118bd8eb990eff (patch) | |
| tree | 2782b785de4347d9d5d16e53a39ad5d9b973a050 /arch/arm/include/asm/arch-fsl-layerscape/config.h | |
| parent | bef238cb1e87f36bfbc7495b9eb933d06ce278ec (diff) | |
| download | u-boot-fsl-qoriq-809d343a1a778e68d519c04e01118bd8eb990eff.tar.xz | |
armv8: ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/config.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index cc25811..ceefe43 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 #define CCI_MN_RNF_NODEID_LIST 0x180 |