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| author | Alex Porosanu <alexandru.porosanu@freescale.com> | 2016-04-29 12:17:58 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-18 15:51:46 (GMT) |
| commit | e99d7193593cf6331ea04cd394a9a4cf18886ef0 (patch) | |
| tree | a187ad9403f8e304c9dd954aec3a8aad51557e08 /arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | |
| parent | 56747bfdbd6f2c5bc391d0c9d5eb20a6a2d50505 (diff) | |
| download | u-boot-fsl-qoriq-e99d7193593cf6331ea04cd394a9a4cf18886ef0.tar.xz | |
arch/arm: add SEC JR0 offset
Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 1d3b336..65b3357 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -77,8 +77,12 @@ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) /* SEC */ -#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull +#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) |