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| author | Tang Yuantian <Yuantian.Tang@nxp.com> | 2016-08-08 07:07:19 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 16:52:35 (GMT) |
| commit | f0beb49290c4e6af7d88895a15a45bbea38318fe (patch) | |
| tree | 7f93b267a01c6672e587c40a5eb40c63c49a06b0 /arch/arm/include/asm/arch-fsl-layerscape/soc.h | |
| parent | 53fec162061811a73c7dab3207f8fdb2343ae289 (diff) | |
| download | u-boot-fsl-qoriq-f0beb49290c4e6af7d88895a15a45bbea38318fe.tar.xz | |
armv8: fsl-lsch2: adjust sata parameter
The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/soc.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 4512732..0729b7f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -60,8 +60,6 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28184d1f -#define AHCI_PORT_PHY_3_CFG 0x0e081509 #define AHCI_PORT_TRANS_CFG 0x08000029 /* AHCI (sata) register map */ |