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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-11-08 12:10:37 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-04 13:12:08 (GMT) |
| commit | 6c70935d7525a4b2b144b49457d2bae85f1d111a (patch) | |
| tree | 663b91f30c048968bcef5a4bf3916b123c51f7ab /arch/arm/include/asm/arch-omap5/omap.h | |
| parent | 39302dcd3013134e936cc76ccee8d1ed5522bfa0 (diff) | |
| download | u-boot-fsl-qoriq-6c70935d7525a4b2b144b49457d2bae85f1d111a.tar.xz | |
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/omap.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 3c2306f..f1d1160 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -239,6 +239,7 @@ struct ctrl_ioregs { u32 ctrl_ddrio_1; u32 ctrl_ddrio_2; u32 ctrl_emif_sdram_config_ext; + u32 ctrl_emif_sdram_config_ext_final; u32 ctrl_ddr_ctrl_ext_0; }; |