diff options
author | Lei Wen <leiwen@marvell.com> | 2011-10-03 20:33:41 (GMT) |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 19:56:37 (GMT) |
commit | 3d90a2adcb1c240c9ef9e9088a4d49a40a3c9504 (patch) | |
tree | dcd7dd00b6fda54e8c7fa9e61f95107bdee2ff9b /arch/arm/include/asm/arch-pantheon | |
parent | 23365af0992e939b12b85050212b44b7dfae3d39 (diff) | |
download | u-boot-fsl-qoriq-3d90a2adcb1c240c9ef9e9088a4d49a40a3c9504.tar.xz |
ARM: pantheon: add mmc definition
Signed-off-by: Lei Wen <leiwen@marvell.com>
Diffstat (limited to 'arch/arm/include/asm/arch-pantheon')
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/config.h | 18 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/cpu.h | 12 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/mfp.h | 12 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/pantheon.h | 7 |
4 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index fd23c97..d10583d 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -47,4 +47,22 @@ #define CONFIG_SYS_I2C_SLAVE 0xfe #endif +/* + * MMC definition + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_CMD_FAT 1 +#define CONFIG_MMC 1 +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_SDHCI 1 +#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1 +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000 +#define CONFIG_MMC_SDMA 1 +#define CONFIG_MV_SDHCI 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +#define CONFIG_SYS_MMC_NUM 2 +#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000} +#endif + #endif /* _PANTHEON_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h index 60955c5..94e8371 100644 --- a/arch/arm/include/asm/arch-pantheon/cpu.h +++ b/arch/arm/include/asm/arch-pantheon/cpu.h @@ -43,6 +43,17 @@ struct panthmpmu_registers { }; /* + * Application Power Management (APMU) Registers + * Refer Register Datasheet 9.2 + */ +struct panthapmu_registers { + u8 pad0[0x0054]; + u32 sd1; /*0x0054*/ + u8 pad1[0x00e0 - 0x054 - 4]; + u32 sd3; /*0x00e0*/ +}; + +/* * APB Clock Reset/Control Registers * Refer Register Datasheet 6.14 */ @@ -77,5 +88,6 @@ struct panthcpu_registers { */ u32 panth_sdram_base(int); u32 panth_sdram_size(int); +int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); #endif /* _PANTHEON_CPU_H */ diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h index e939196..b868ab8 100644 --- a/arch/arm/include/asm/arch-pantheon/mfp.h +++ b/arch/arm/include/asm/arch-pantheon/mfp.h @@ -38,6 +38,18 @@ #define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) /* More macros can be defined here... */ +#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST) +#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST) +#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST) +#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST) +#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST) +#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST) +#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM) #define MFP_PIN_MAX 117 #endif diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h index c7fe646..d5e9ba0 100644 --- a/arch/arm/include/asm/arch-pantheon/pantheon.h +++ b/arch/arm/include/asm/arch-pantheon/pantheon.h @@ -32,6 +32,12 @@ /* Functional Clock Selection Mask */ #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) +/* Common APMU register bit definitions */ +#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */ +#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/ +#define APMU_PERI_RST (1<<1) /* Peripheral Reset */ +#define APMU_AXI_RST (1<<0) /* AXI Reset */ + /* Register Base Addresses */ #define PANTHEON_DRAM_BASE 0xB0000000 #define PANTHEON_TIMER_BASE 0xD4014000 @@ -42,6 +48,7 @@ #define PANTHEON_GPIO_BASE 0xD4019000 #define PANTHEON_MFPR_BASE 0xD401E000 #define PANTHEON_MPMU_BASE 0xD4050000 +#define PANTHEON_APMU_BASE 0xD4282800 #define PANTHEON_CPU_BASE 0xD4282C00 #endif /* _PANTHEON_H */ |