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| author | Tom Warren <twarren.nvidia@gmail.com> | 2011-04-14 12:09:39 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-04-27 17:38:09 (GMT) |
| commit | 1436d510764b5409daf0ff4948df66500a70869b (patch) | |
| tree | dee5b6f8beb82955533899f22b1be0d2df4fba1f /arch/arm/include/asm/arch-tegra2/clk_rst.h | |
| parent | 6445a3051efadcac1264998cb6387cd1aec2e935 (diff) | |
| download | u-boot-fsl-qoriq-1436d510764b5409daf0ff4948df66500a70869b.tar.xz | |
arm: Tegra2: Add missing PLLX init
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra2/clk_rst.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra2/clk_rst.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index d67a5d7..bd8ad2c 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -160,8 +160,8 @@ struct clk_rst_ctlr { #define PLL_DIVP (1 << 20) /* post divider, b22:20 */ #define PLL_DIVM 0x0C /* input divider, b4:0 */ -#define SWR_UARTD_RST (1 << 2) -#define CLK_ENB_UARTD (1 << 2) +#define SWR_UARTD_RST (1 << 1) +#define CLK_ENB_UARTD (1 << 1) #define SWR_UARTA_RST (1 << 6) #define CLK_ENB_UARTA (1 << 6) @@ -189,4 +189,6 @@ struct clk_rst_ctlr { #define CPU0_CLK_STP (1 << 8) #define CPU1_CLK_STP (1 << 9) +#define CPCON (1 << 8) + #endif /* CLK_RST_H */ |