diff options
author | Stephen Warren <swarren@nvidia.com> | 2014-01-24 19:46:07 (GMT) |
---|---|---|
committer | Tom Warren <twarren@nvidia.com> | 2014-02-03 16:46:46 (GMT) |
commit | 41cd530d6d9b4fb3c2ab475cb92f1242400b5fb1 (patch) | |
tree | 3beb627bd527d95316667ab941e1c00894889c33 /arch/arm/include/asm/arch-tegra | |
parent | a73ca4789fddce35936dd8decb1522f08b6cb620 (diff) | |
download | u-boot-fsl-qoriq-41cd530d6d9b4fb3c2ab475cb92f1242400b5fb1.tar.xz |
ARM: tegra: misc cleanups triggered by Tegra124 review
Use a named constant for the PLL lock bit in enable_cpu_clocks().
Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra')
-rw-r--r-- | arch/arm/include/asm/arch-tegra/clk_rst.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 021cfcc..cc60825 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -160,6 +160,9 @@ struct clk_rst_ctlr { #define PLL_BASE_OVRRIDE_MASK (1U << 28) +#define PLL_LOCK_SHIFT 27 +#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) + #define PLL_DIVP_SHIFT 20 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) |