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author | Michal Simek <michal.simek@xilinx.com> | 2013-06-17 12:37:01 (GMT) |
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committer | Michal Simek <michal.simek@xilinx.com> | 2013-08-12 06:59:55 (GMT) |
commit | 148ba55cc618eaca19d7c86bdc003a7a71ee3a92 (patch) | |
tree | b16460d9e03b64975ea70c2629584c401991f466 /arch/arm/include/asm/arch-zynq | |
parent | a78dac79ede7fbb4c9e816abc879655540c3f076 (diff) | |
download | u-boot-fsl-qoriq-148ba55cc618eaca19d7c86bdc003a7a71ee3a92.tar.xz |
zynq: Add new ddrc driver for ECC support
The first 1MB is not initialized by first stage bootloader.
Check if memory is setup to 16bit mode and ECC is enabled.
If it is, clear the first 1MB.
Also u-boot should report only the half size of memory.
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/include/asm/arch-zynq')
-rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-zynq/sys_proto.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 25f0e3d..ca56d8a 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -17,6 +17,7 @@ #define ZYNQ_SDHCI_BASEADDR1 0xE0101000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 +#define ZYNQ_DDRC_BASEADDR 0xF8006000 /* Reflect slcr offsets */ struct slcr_regs { @@ -84,4 +85,11 @@ struct scu_regs { #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR) +struct ddrc_regs { + u32 ddrc_ctrl; /* 0x0 */ + u32 reserved[60]; + u32 ecc_scrub; /* 0xF4 */ +}; +#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 19a4eec..110de90 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -14,6 +14,7 @@ extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_idcode(void); +extern void zynq_ddrc_init(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); |